15 Commits

Author	SHA1	Message	Date
PurplePower	3e3c8ba6c0	board updates and fixes ... - now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently	2024-11-18 10:50:45 +08:00
PurplePower	b9294c0bd1	added c source files back	2024-01-23 21:35:09 +08:00
PurplePower	b3738b8f63	Updated z710 README and vitis script ... - skipped a redundant `paltform generate` in vitis_prj_run.tcl - updated z710 README.md to be more detailed	2024-01-19 15:40:51 +08:00
PurplePower	0a8f2ecffc	updated readme for z710 board burning	2024-01-13 11:54:24 +08:00
PurplePower	ef4a567f22	Updated readme in z710 board burning	2024-01-13 11:34:17 +08:00
PurplePower	d79780a480	Fixed vivado script import path error	2023-12-27 14:01:29 +08:00
PurplePower	844cb062c2	Deleted useless verilog files	2023-12-26 01:18:54 +08:00
PurplePower	5ecb75157a	added vivado-vitis uart workflow to lab3	2023-12-25 23:40:26 +08:00
PurplePower	bcd11625a6	Fixed generate bitstream bug ... copy not rename so vivado GUI still finds the .bit file	2023-12-25 11:53:20 +08:00
PurplePower	2a6899729b	Fixed Z7-10 generator duplicate file directory	2023-12-23 00:52:34 +08:00
TOKISAKIX\21168	42bcfd9b9c	finished lab3	2023-12-12 23:07:53 +08:00
TOKISAKIX\21168	90452baed2	add lab3 file	2023-12-12 22:24:33 +08:00
TOKISAKIX\21168	2bce97ff4e	add file	2023-12-11 22:20:48 +08:00
TOKISAKIX\21168	e720a0dfc2	add csrc	2023-12-11 21:54:53 +08:00
TOKISAKIX\21168	910ee11168	init repo	2023-12-11 21:50:22 +08:00