Commit Graph

5 Commits

Author SHA1 Message Date
PurplePower
b9865cd612 Lab3 pipelined CPU renewed
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
2025-08-14 16:55:53 +08:00
PurplePower
3e3c8ba6c0 board updates and fixes
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
2024-11-18 10:50:45 +08:00
PurplePower
844cb062c2 Deleted useless verilog files 2023-12-26 01:18:54 +08:00
PurplePower
bcd11625a6 Fixed generate bitstream bug
copy not rename so vivado GUI still finds the .bit file
2023-12-25 11:53:20 +08:00
TOKISAKIX\21168
73df6caf1c add mini-yatcpu 2023-12-12 11:03:06 +08:00