diff --git a/lab1/csrc/say_goodbye.c b/lab1/csrc/say_goodbye.c
index 6848120..3f551aa 100644
--- a/lab1/csrc/say_goodbye.c
+++ b/lab1/csrc/say_goodbye.c
@@ -16,8 +16,8 @@ void waste_some_time(int cycle) {
 int main() {
 
     // const char* s = "abcd";
-    const char* s = "Never gonna give you up~ Never gonna let you down~\n\
-    Never gonna run around and~ desert you~\n";
+    const char* s = "Never gonna give you up~ Never gonna let you down~\n"
+    "Never gonna run around and~ desert you~\n";
 
     while (1) {
       
diff --git a/lab1/src/main/resources/say_goodbye.asmbin b/lab1/src/main/resources/say_goodbye.asmbin
index d72478c..23ece47 100644
Binary files a/lab1/src/main/resources/say_goodbye.asmbin and b/lab1/src/main/resources/say_goodbye.asmbin differ
diff --git a/lab1/vivado/z710v1.3/README.md b/lab1/vivado/z710v1.3/README.md
index 84bed4e..9461d6a 100644
--- a/lab1/vivado/z710v1.3/README.md
+++ b/lab1/vivado/z710v1.3/README.md
@@ -78,7 +78,6 @@ vivado -mode batch -source ./program_device.tcl
 
 ## For Maintainers
 
-Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。
 本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的：
 
 - reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。
diff --git a/lab2/csrc/say_goodbye.c b/lab2/csrc/say_goodbye.c
index 6848120..3f551aa 100644
--- a/lab2/csrc/say_goodbye.c
+++ b/lab2/csrc/say_goodbye.c
@@ -16,8 +16,8 @@ void waste_some_time(int cycle) {
 int main() {
 
     // const char* s = "abcd";
-    const char* s = "Never gonna give you up~ Never gonna let you down~\n\
-    Never gonna run around and~ desert you~\n";
+    const char* s = "Never gonna give you up~ Never gonna let you down~\n"
+    "Never gonna run around and~ desert you~\n";
 
     while (1) {
       
diff --git a/lab2/src/main/resources/say_goodbye.asmbin b/lab2/src/main/resources/say_goodbye.asmbin
index d72478c..23ece47 100644
Binary files a/lab2/src/main/resources/say_goodbye.asmbin and b/lab2/src/main/resources/say_goodbye.asmbin differ
diff --git a/lab2/vivado/z710v1.3/README.md b/lab2/vivado/z710v1.3/README.md
index 84bed4e..9461d6a 100644
--- a/lab2/vivado/z710v1.3/README.md
+++ b/lab2/vivado/z710v1.3/README.md
@@ -78,7 +78,6 @@ vivado -mode batch -source ./program_device.tcl
 
 ## For Maintainers
 
-Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。
 本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的：
 
 - reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。
diff --git a/lab3/csrc/say_goodbye.c b/lab3/csrc/say_goodbye.c
index 6848120..3f551aa 100644
--- a/lab3/csrc/say_goodbye.c
+++ b/lab3/csrc/say_goodbye.c
@@ -16,8 +16,8 @@ void waste_some_time(int cycle) {
 int main() {
 
     // const char* s = "abcd";
-    const char* s = "Never gonna give you up~ Never gonna let you down~\n\
-    Never gonna run around and~ desert you~\n";
+    const char* s = "Never gonna give you up~ Never gonna let you down~\n"
+    "Never gonna run around and~ desert you~\n";
 
     while (1) {
       
diff --git a/lab3/src/main/resources/say_goodbye.asmbin b/lab3/src/main/resources/say_goodbye.asmbin
index d72478c..23ece47 100644
Binary files a/lab3/src/main/resources/say_goodbye.asmbin and b/lab3/src/main/resources/say_goodbye.asmbin differ
diff --git a/lab3/vivado/z710v1.3/README.md b/lab3/vivado/z710v1.3/README.md
index 84bed4e..9461d6a 100644
--- a/lab3/vivado/z710v1.3/README.md
+++ b/lab3/vivado/z710v1.3/README.md
@@ -78,7 +78,6 @@ vivado -mode batch -source ./program_device.tcl
 
 ## For Maintainers
 
-Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。
 本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的：
 
 - reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。
diff --git a/lab4/csrc/say_goodbye.c b/lab4/csrc/say_goodbye.c
index 6848120..3f551aa 100644
--- a/lab4/csrc/say_goodbye.c
+++ b/lab4/csrc/say_goodbye.c
@@ -16,8 +16,8 @@ void waste_some_time(int cycle) {
 int main() {
 
     // const char* s = "abcd";
-    const char* s = "Never gonna give you up~ Never gonna let you down~\n\
-    Never gonna run around and~ desert you~\n";
+    const char* s = "Never gonna give you up~ Never gonna let you down~\n"
+    "Never gonna run around and~ desert you~\n";
 
     while (1) {
       
diff --git a/lab4/src/main/resources/say_goodbye.asmbin b/lab4/src/main/resources/say_goodbye.asmbin
index d72478c..23ece47 100644
Binary files a/lab4/src/main/resources/say_goodbye.asmbin and b/lab4/src/main/resources/say_goodbye.asmbin differ
diff --git a/lab4/vivado/z710v1.3/README.md b/lab4/vivado/z710v1.3/README.md
index 84bed4e..9461d6a 100644
--- a/lab4/vivado/z710v1.3/README.md
+++ b/lab4/vivado/z710v1.3/README.md
@@ -78,7 +78,6 @@ vivado -mode batch -source ./program_device.tcl
 
 ## For Maintainers
 
-Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。
 本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的：
 
 - reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。