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finished lab4

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TOKISAKIX\21168
2023-12-11 23:44:26 +08:00
parent cfa7e2d2ab
commit cda1a478ed
4 changed files with 2 additions and 11230 deletions
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120
lab4/src/main/scala/bus/AXI4Lite.scala
View File

@@ -153,62 +153,7 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module {
val BRESP = WireInit(0.U(AXI4Lite.respWidth))
io.channels.write_response_channel.BRESP := BRESP
//lab4(BUS)
switch(state) {
is(AXI4LiteStates.Idle) {
read := false.B
write := false.B
RVALID := false.B
BVALID := false.B
when(io.channels.write_address_channel.AWVALID) {
state := AXI4LiteStates.WriteAddr
}.elsewhen(io.channels.read_address_channel.ARVALID) {
state := AXI4LiteStates.ReadAddr
}
}
is(AXI4LiteStates.ReadAddr) {
ARREADY := true.B
when(io.channels.read_address_channel.ARVALID && ARREADY) {
state := AXI4LiteStates.ReadData
addr := io.channels.read_address_channel.ARADDR
read := true.B
ARREADY := false.B
}
}
is(AXI4LiteStates.ReadData) {
RVALID := io.bundle.read_valid
when(io.channels.read_data_channel.RREADY && RVALID) {
state := AXI4LiteStates.Idle
RVALID := false.B
}
}
is(AXI4LiteStates.WriteAddr) {
AWREADY := true.B
when(io.channels.write_address_channel.AWVALID && AWREADY) {
addr := io.channels.write_address_channel.AWADDR
state := AXI4LiteStates.WriteData
AWREADY := false.B
}
}
is(AXI4LiteStates.WriteData) {
WREADY := true.B
when(io.channels.write_data_channel.WVALID && WREADY) {
state := AXI4LiteStates.WriteResp
write_data := io.channels.write_data_channel.WDATA
write_strobe := io.channels.write_data_channel.WSTRB.asBools
write := true.B
WREADY := false.B
}
}
is(AXI4LiteStates.WriteResp) {
WREADY := false.B
BVALID := true.B
when(io.channels.write_response_channel.BREADY && BVALID) {
state := AXI4LiteStates.Idle
write := false.B
BVALID := false.B
}
}
}
}
class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
@@ -247,66 +192,5 @@ class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
val BREADY = RegInit(false.B)
io.channels.write_response_channel.BREADY := BREADY
//lab4(BUS)
switch(state) {
is(AXI4LiteStates.Idle) {
WVALID := false.B
AWVALID := false.B
ARVALID := false.B
RREADY := false.B
read_valid := false.B
write_valid := false.B
when(io.bundle.write) {
state := AXI4LiteStates.WriteAddr
addr := io.bundle.address
write_data := io.bundle.write_data
write_strobe := io.bundle.write_strobe
}.elsewhen(io.bundle.read) {
state := AXI4LiteStates.ReadAddr
addr := io.bundle.address
}
}
is(AXI4LiteStates.ReadAddr) {
ARVALID := true.B
io.channels.read_address_channel.ARADDR := addr
when(io.channels.read_address_channel.ARREADY && ARVALID) {
state := AXI4LiteStates.ReadData
io.channels.read_address_channel.ARADDR := addr
ARVALID := false.B
}
}
is(AXI4LiteStates.ReadData) {
when(io.channels.read_data_channel.RVALID && io.channels.read_data_channel.RRESP === 0.U) {
state := AXI4LiteStates.Idle
read_valid := true.B
RREADY := true.B
read_data := io.channels.read_data_channel.RDATA
}
}
is(AXI4LiteStates.WriteAddr) {
AWVALID := true.B
io.channels.write_address_channel.AWADDR := addr
when(io.channels.write_address_channel.AWREADY && AWVALID) {
state := AXI4LiteStates.WriteData
io.channels.write_address_channel.AWADDR := addr
AWVALID := false.B
}
}
is(AXI4LiteStates.WriteData) {
WVALID := true.B
io.channels.write_address_channel.AWADDR := addr
when(io.channels.write_data_channel.WREADY && WVALID) {
io.channels.write_address_channel.AWADDR := addr
state := AXI4LiteStates.WriteResp
WVALID := false.B
}
}
is(AXI4LiteStates.WriteResp) {
BREADY := true.B
when(io.channels.write_response_channel.BVALID && BREADY) {
state := AXI4LiteStates.Idle
write_valid := true.B
BREADY := false.B
}
}
}
}

435
lab4/verilog/z710/Top.anno.json
View File

@@ -1,435 +0,0 @@
[
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave",
"duplicate":"~Top|Top/uart:Uart/slave:AXI4LiteSlave",
"index":0.0
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction:PipelineRegister",
"index":0.12
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_1",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction_address:PipelineRegister_1",
"index":0.13333333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_2",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/interrupt_flag:PipelineRegister_2",
"index":0.14666666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_3",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction:PipelineRegister",
"index":0.18666666666666668
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_4",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction_address:PipelineRegister_1",
"index":0.2
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_5",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_enable:PipelineRegister_5",
"index":0.21333333333333335
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_6",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_address:PipelineRegister_6",
"index":0.22666666666666666
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_7",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_source:PipelineRegister_7",
"index":0.24
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_8",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg1_data:PipelineRegister_2",
"index":0.25333333333333335
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_9",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg2_data:PipelineRegister_2",
"index":0.26666666666666666
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_10",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/immediate:PipelineRegister_2",
"index":0.28
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_11",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop1_source:PipelineRegister_5",
"index":0.29333333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_12",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop2_source:PipelineRegister_5",
"index":0.30666666666666664
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_13",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_write_enable:PipelineRegister_5",
"index":0.32
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_15",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_read_enable:PipelineRegister_5",
"index":0.3466666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_16",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_write_enable:PipelineRegister_5",
"index":0.36
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_17",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_read_data:PipelineRegister_2",
"index":0.37333333333333335
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_18",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_enable:PipelineRegister_5",
"index":0.44
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_19",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_source:PipelineRegister_7",
"index":0.4533333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_20",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_address:PipelineRegister_6",
"index":0.4666666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_21",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction_address:PipelineRegister_2",
"index":0.48
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_22",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction:PipelineRegister_2",
"index":0.49333333333333335
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_23",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg1_data:PipelineRegister_2",
"index":0.5066666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_24",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg2_data:PipelineRegister_2",
"index":0.52
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_25",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/alu_result:PipelineRegister_2",
"index":0.5333333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_26",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_read_enable:PipelineRegister_5",
"index":0.5466666666666666
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_27",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_write_enable:PipelineRegister_5",
"index":0.56
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_28",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/csr_read_data:PipelineRegister_2",
"index":0.5733333333333334
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_29",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/alu_result:PipelineRegister_2",
"index":0.6133333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_30",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/memory_read_data:PipelineRegister_2",
"index":0.6266666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_31",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_enable:PipelineRegister_5",
"index":0.64
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_32",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_source:PipelineRegister_7",
"index":0.6533333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_33",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_address:PipelineRegister_6",
"index":0.6666666666666666
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_34",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/instruction_address:PipelineRegister_2",
"index":0.68
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_35",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/csr_read_data:PipelineRegister_2",
"index":0.6933333333333334
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/axi4_master:AXI4LiteMaster",
"index":0.7733333333333333
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_1",
"duplicate":"~Top|Top/mem:Memory/slave:AXI4LiteSlave_1",
"index":0.8266666666666667
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_2",
"duplicate":"~Top|Top/timer:Timer/slave:AXI4LiteSlave",
"index":0.8533333333333334
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_3",
"duplicate":"~Top|Top/dummy:DummySlave/slave:AXI4LiteSlave_1",
"index":0.88
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster_1",
"duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster",
"index":0.92
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster_2",
"duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster",
"index":0.9733333333333334
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteMaster.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"firrtl.annotations.MemorySynthInit$"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteSlave_1.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteSlave.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.MemoryAccessStates",
"definition":{
"Idle":0,
"Read":1,
"Write":2,
"ReadWrite":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.MemoryAccess.mem_access_state",
"enumTypeName":"riscv.core.fivestage.MemoryAccessStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_33",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_31",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_29",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_27",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_25",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_23",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_21",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_17",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_15",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_13",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_11",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_9",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_7",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_5",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_3",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_1",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl.io_alu_funct",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.ALUFunctions",
"definition":{
"sll":3,
"sra":9,
"or":6,
"xor":5,
"slt":4,
"sub":2,
"add":1,
"sltu":10,
"and":7,
"srl":8,
"zero":0
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALU.io_func",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"bus.AXI4LiteStates",
"definition":{
"ReadData":2,
"WriteAddr":3,
"WriteResp":5,
"Idle":0,
"WriteData":4,
"ReadAddr":1
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"board.z710.BootStates",
"definition":{
"Init":0,
"Loading":1,
"BusWait":2,
"Finished":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.Top.boot_state",
"enumTypeName":"board.z710.BootStates"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"verilog/z710"
},
{
"class":"firrtl.annotations.MemoryFileInlineAnnotation",
"target":"~Top|InstructionROM>mem",
"filename":"/root/yatcpu/lab4/verilog/say_goodbye.asmbin.txt",
"hexOrBinary":"h"
}
]

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lab4/verilog/z710/Top.fir
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lab4/verilog/z710/Top.v
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