From cba231d592af1236cd77902e5ac1712fa8dae573 Mon Sep 17 00:00:00 2001
From: "TOKISAKIX\\21168" <2116884726@qq.com>
Date: Tue, 12 Dec 2023 00:34:29 +0800
Subject: [PATCH] finished lab2
---
README.md | 11 +
lab2/src/main/scala/board/z710/z710/Top.scala | 103 ++++
lab2/src/test/scala/riscv/BoardTest.scala | 30 +-
lab2/vivado/z710/generate_and_program.tcl | 17 +
lab2/vivado/z710/generate_bitstream.tcl | 57 +++
lab2/vivado/z710/helloworld.c | 139 ++++++
lab2/vivado/z710/open_project.tcl | 33 ++
lab2/vivado/z710/program_device.tcl | 24 +
.../z710/riscv-z710/design_1_wrapper.xsa | Bin 0 -> 346664 bytes
.../sources_1/bd/design_1/design_1.bd | 459 ++++++++++++++++++
.../bd/design_1/hdl/design_1_wrapper.v | 116 +++++
lab2/vivado/z710/riscv-z710/riscv-z710.xpr | 376 ++++++++++++++
lab2/vivado/z710/run_simulation.tcl | 24 +
lab2/vivado/z710/z710.xdc | 216 +++++++++
start_cpu.bat | 1 -
15 files changed, 1590 insertions(+), 16 deletions(-)
create mode 100644 lab2/src/main/scala/board/z710/z710/Top.scala
create mode 100644 lab2/vivado/z710/generate_and_program.tcl
create mode 100644 lab2/vivado/z710/generate_bitstream.tcl
create mode 100644 lab2/vivado/z710/helloworld.c
create mode 100644 lab2/vivado/z710/open_project.tcl
create mode 100644 lab2/vivado/z710/program_device.tcl
create mode 100644 lab2/vivado/z710/riscv-z710/design_1_wrapper.xsa
create mode 100644 lab2/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/design_1.bd
create mode 100644 lab2/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
create mode 100644 lab2/vivado/z710/riscv-z710/riscv-z710.xpr
create mode 100644 lab2/vivado/z710/run_simulation.tcl
create mode 100644 lab2/vivado/z710/z710.xdc
delete mode 100644 start_cpu.bat
diff --git a/README.md b/README.md
index f53c9de..5483963 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,12 @@
# YatCPU
+
+本仓库由 [Tokisakix](https://github.com/Tokisakix)、[PurplePower](https://github.com/PurplePower)、[Han Huang](https://github.com/HHTheBest) 在 [2022-fall-yatcpu-repo](https://github.com/hrpccs/2022-fall-yatcpu-repo) 的基础上结合教学实情整理而来
+
+本整合仓库具有以下特点：
+- 已提前用 cmake 编译好测试文件，无再运行 build.bat 或 build.sh
+- 完全保留了原教学仓库的代码段填空设置和项目架构，代码搬运便捷
+- 已编写好烧板脚本，支持 ZYBO-Z710 开发板的一键烧录，学生只需要把精力集中在 CPU 的编写即可
+
+YatCPU 文档地址[点击此处](https://yatcpu.sysu.tech)
+
+(能求个 star⭐ 吗 QAQ ~)
\ No newline at end of file
diff --git a/lab2/src/main/scala/board/z710/z710/Top.scala b/lab2/src/main/scala/board/z710/z710/Top.scala
new file mode 100644
index 0000000..97864a5
--- /dev/null
+++ b/lab2/src/main/scala/board/z710/z710/Top.scala
@@ -0,0 +1,103 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.z710
+
+import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.util.Cat
+import peripheral._
+import riscv.Parameters
+import riscv.core.{CPU, ProgramCounter}
+
+class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
+ val io = IO(new Bundle() {
+ val tx = Output(Bool())
+ val rx = Input(Bool())
+
+ val led = Output(Bool()) // z710 has few LEDs, use one for running indicator
+ })
+ val mem = Module(new Memory(Parameters.MemorySizeInWords))
+ // val hdmi_display = Module(new HDMIDisplay)
+ // val display = Module(new CharacterDisplay)
+ val timer = Module(new Timer)
+ val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
+ val dummy = Module(new Dummy)
+
+ // display.io.bundle <> dummy.io.bundle
+ mem.io.bundle <> dummy.io.bundle
+ mem.io.debug_read_address := 0.U
+ timer.io.bundle <> dummy.io.bundle
+ uart.io.bundle <> dummy.io.bundle
+ io.tx := uart.io.txd
+ uart.io.rxd := io.rx
+
+ val instruction_rom = Module(new InstructionROM(binaryFilename))
+ val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+ rom_loader.io.rom_data := instruction_rom.io.data
+ rom_loader.io.load_address := Parameters.EntryAddress
+ instruction_rom.io.address := rom_loader.io.rom_address
+
+ val CPU_clkdiv = RegInit(UInt(2.W),0.U)
+ val CPU_tick = Wire(Bool())
+ val CPU_next = Wire(UInt(2.W))
+ CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+ CPU_tick := CPU_clkdiv === 0.U
+ CPU_clkdiv := CPU_next
+
+ withClock(CPU_tick.asClock) {
+ val cpu = Module(new CPU)
+ cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+ cpu.io.csr_regs_debug_read_address := 0.U
+ cpu.io.regs_debug_read_address := 0.U
+ cpu.io.instruction_valid := rom_loader.io.load_finished
+ mem.io.instruction_address := cpu.io.instruction_address
+ cpu.io.instruction := mem.io.instruction
+
+ when(!rom_loader.io.load_finished) {
+ rom_loader.io.bundle <> mem.io.bundle
+ cpu.io.memory_bundle.read_data := 0.U
+ }.otherwise {
+ rom_loader.io.bundle.read_data := 0.U
+ when(cpu.io.deviceSelect === 4.U) {
+ cpu.io.memory_bundle <> timer.io.bundle
+ }.elsewhen(cpu.io.deviceSelect === 2.U) { // deviceSelect = highest 3 bits of address, thus 0x4000_0000 is mapped to UART
+ cpu.io.memory_bundle <> uart.io.bundle
+ }.otherwise {
+ cpu.io.memory_bundle <> mem.io.bundle
+ }
+ }
+ }
+
+ // LED, blinks every second
+ val clock_freq = 40_000_000.U
+ val led_count = RegInit(0.U(32.W))
+ when (led_count >= clock_freq) {
+ led_count := 0.U
+ }.otherwise {
+ led_count := led_count + 1.U
+ }
+ io.led := (led_count >= (clock_freq >> 1))
+
+
+
+}
+
+object VerilogGenerator extends App {
+ (new ChiselStage).execute(
+ Array("-X", "verilog", "-td", "verilog/z710"),
+ Seq(ChiselGeneratorAnnotation(() => new Top("say_goodbye.asmbin"))) // program to run on CPU
+ )
+}
\ No newline at end of file
diff --git a/lab2/src/test/scala/riscv/BoardTest.scala b/lab2/src/test/scala/riscv/BoardTest.scala
index 40bd459..46e0621 100644
--- a/lab2/src/test/scala/riscv/BoardTest.scala
+++ b/lab2/src/test/scala/riscv/BoardTest.scala
@@ -1,25 +1,25 @@
-package riscv
+package riscv.singlecycle
-import board.z710.Top
-
-import riscv.{Parameters, TestAnnotations}
+import board.basys3.BootStates
import chisel3._
-import chisel3.util.{is, switch}
import chiseltest._
import org.scalatest.flatspec.AnyFlatSpec
+
+import riscv.{Parameters, TestAnnotations}
+
import board.z710.Top
-class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
- behavior of "Board simulation"
- it should "say goodbye " in {
- test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
-
- for (i <- 1 to 50000) {
- c.clock.step(5)
- c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
- }
- }
+class BoardSayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+ behavior of "Board Single"
+ it should "say goodbye" in {
+ test(new Top("say_goodbye.asmbin")).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation))
+ { c =>
+ for (i <- 1 to 200) {
+ c.clock.step(1000)
+ c.io.rx.poke((i % 2).B) // Avoid timeout
+ }
+ }
}
}
diff --git a/lab2/vivado/z710/generate_and_program.tcl b/lab2/vivado/z710/generate_and_program.tcl
new file mode 100644
index 0000000..71df1af
--- /dev/null
+++ b/lab2/vivado/z710/generate_and_program.tcl
@@ -0,0 +1,17 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+source generate_bitstream.tcl
+source program_device.tcl
\ No newline at end of file
diff --git a/lab2/vivado/z710/generate_bitstream.tcl b/lab2/vivado/z710/generate_bitstream.tcl
new file mode 100644
index 0000000..0a025be
--- /dev/null
+++ b/lab2/vivado/z710/generate_bitstream.tcl
@@ -0,0 +1,57 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source open_project.tcl
+
+while 1 {
+ if { [catch {launch_runs synth_1 -jobs 4 } ] } {
+ regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
+ if { [string equal $code "12-978"] } {
+ puts "Already generated and up-to-date"
+ break
+ } elseif { [string equal $code "17-69"] } {
+ puts "Out of date, reset runs"
+ reset_runs synth_1
+ continue
+ } else {
+ puts "UNKNOWN ERROR!!! $errorInfo"
+ exit
+ }
+ }
+ break
+}
+
+wait_on_run synth_1
+
+while 1 {
+ if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
+ regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
+ if { [string equal $code "12-978"] } {
+ puts "Already generated and up-to-date"
+ break
+ } elseif { [string equal $code "12-1088"] } {
+ puts "Out of date, reset runs"
+ reset_runs impl_1
+ continue
+ } else {
+ puts "UNKNOWN ERROR!!! $errorInfo"
+ exit
+ }
+ }
+ break
+}
+
+wait_on_run impl_1
+
+file rename riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit
\ No newline at end of file
diff --git a/lab2/vivado/z710/helloworld.c b/lab2/vivado/z710/helloworld.c
new file mode 100644
index 0000000..1f04639
--- /dev/null
+++ b/lab2/vivado/z710/helloworld.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE BAUD RATE |
+ * ------------------------------------------------
+ * uartns550 9600
+ * uartlite Configurable only in HW design
+ * ps7_uart 115200 (configured by bootrom/bsp)
+ */
+
+#include
+#include "platform.h"
+#include "xil_printf.h"
+//#include "xuartps_hw.h" // already include in xuartps.h
+#include "xuartps.h"
+#include "xparameters.h"
+
+XUartPs uart_ps; // instance of the UART device
+
+
+
+
+int main()
+{
+ init_platform();
+ xil_printf("\nHello World\n\r");
+
+
+ // test on UART ps
+ int BUFFER_SIZE = 16; // do not set too much to overflow FIFO
+ char send_buffer[BUFFER_SIZE + 1];
+ char recv_buffer[BUFFER_SIZE + 1];
+ int status = 0;
+ XUartPs_Config *config;
+
+
+ for (int i = 0; i < BUFFER_SIZE; i++) send_buffer[i] = i % 256;
+
+ config = XUartPs_LookupConfig(XPAR_XUARTPS_0_BASEADDR); // CHANGE UART PORT HERE!!!
+ if (config == NULL) {
+ printf("Error in config lookup!\n");
+ return XST_FAILURE;
+ }
+
+
+ status = XUartPs_CfgInitialize(&uart_ps, config, config->BaseAddress);
+ if (status != XST_SUCCESS) {
+ printf("Error in cfg initialize!\n");
+ return XST_FAILURE;
+ }
+ XUartPs_SetBaudRate(&uart_ps, 115200);
+
+ /* Check hardware build. */
+ status = XUartPs_SelfTest(&uart_ps);
+ if (status != XST_SUCCESS) {
+ printf("Error in self test!\n");
+ return XST_FAILURE;
+ }
+
+
+ /* Configure UART mode */
+ int mode = XUartPs_ReadReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET);
+ printf("original mode = 0x%x\n", mode);
+ XUartPs_WriteReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET,
+ (XUARTPS_MR_STOPMODE_2_BIT | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT));
+
+
+
+ XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
+
+
+
+
+ int recv_cnt = 0;
+ while (1) {
+ int recved = XUartPs_Recv(&uart_ps, (u8*)(recv_buffer + 0), BUFFER_SIZE);
+ recv_cnt += recved;
+ recv_buffer[recv_cnt] = 0; // end
+ if (recv_cnt >= 1) {
+// printf("%s", recv_buffer);
+// printf("%i\n", recv_buffer[0]);
+
+ /* print string manually */
+ for (int j = 0; j < BUFFER_SIZE; j++) {
+ if (recv_buffer[j] != 0) {
+ printf("%c", recv_buffer[j]);
+ } else {
+ break;
+ }
+ }
+
+ recv_cnt = 0;
+ }
+ }
+
+ /* Restore to normal mode. */
+ XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
+
+
+ cleanup_platform();
+ return 0;
+}
diff --git a/lab2/vivado/z710/open_project.tcl b/lab2/vivado/z710/open_project.tcl
new file mode 100644
index 0000000..f758198
--- /dev/null
+++ b/lab2/vivado/z710/open_project.tcl
@@ -0,0 +1,33 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+
+# set variables
+set project_dir riscv-z710
+set project_name riscv-z710
+set part xc7z010clg400-1
+set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v}
+set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v}
+
+# open the project. will create one if it doesn't exist
+if {[file exist $project_dir]} {
+ # check that it's a directory
+ if {! [file isdirectory $project_dir]} {
+ puts "$project_dir exists, but it's a file"
+ }
+ open_project $project_dir/$project_name.xpr -part $part
+} else {
+ source riscv-z710.tcl
+}
\ No newline at end of file
diff --git a/lab2/vivado/z710/program_device.tcl b/lab2/vivado/z710/program_device.tcl
new file mode 100644
index 0000000..dc784fe
--- /dev/null
+++ b/lab2/vivado/z710/program_device.tcl
@@ -0,0 +1,24 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_server [current_hw_server]
+open_hw_target [lindex [get_hw_targets] 0]
+set_property PROGRAM.FILE {./riscv-z710/riscv-z710.runs/impl_1/Top.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+close_hw_target
diff --git a/lab2/vivado/z710/riscv-z710/design_1_wrapper.xsa b/lab2/vivado/z710/riscv-z710/design_1_wrapper.xsa
new file mode 100644
index 0000000000000000000000000000000000000000..b7827744acb1748902f0a60b068c87f72541b80d
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