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Lab3 pipelined CPU renewed

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- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
This commit is contained in:
PurplePower
2025-08-14 16:55:53 +08:00
parent 110132ff95
commit b9865cd612
33 changed files with 494 additions and 98 deletions
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4
lab4/verilog/verilator/sim_main.cpp
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@@ -121,12 +121,12 @@ class Simulator {
if (auto it = std::find(args.begin(), args.end(), "-memory");
it != args.end()) {
memory_words = std::stoul(*(it + 1));
memory_words = std::stoull(*(it + 1));
}
if (auto it = std::find(args.begin(), args.end(), "-time");
it != args.end()) {
max_sim_time = std::stoul(*(it + 1));
max_sim_time = std::stoull(*(it + 1));
}
if (auto it = std::find(args.begin(), args.end(), "-vcd");