Lab3 pipelined CPU renewed

- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding

lab2/src/main/scala/board/verilator/Top.scala

@@ -24,22 +24,24 @@ class Top extends Module {
   val io = IO(new CPUBundle)
 
   val cpu = Module(new CPU)
-
-  io.deviceSelect := 0.U
   cpu.io.regs_debug_read_address := io.regs_debug_read_address
   cpu.io.csr_regs_debug_read_address := io.csr_regs_debug_read_address
   io.csr_regs_debug_read_data := cpu.io.csr_regs_debug_read_data
   io.regs_debug_read_data := cpu.io.regs_debug_read_data
 
+  // intercept UART signals
+  io.deviceSelect := cpu.io.deviceSelect
+
+  // CPU instruction input is controlled by external codes
   io.memory_bundle <> cpu.io.memory_bundle
   io.instruction_address := cpu.io.instruction_address
   cpu.io.instruction := io.instruction
+  cpu.io.instruction_valid := io.instruction_valid
 
   cpu.io.interrupt_flag := io.interrupt_flag
-  cpu.io.instruction_valid := io.instruction_valid
 }
 
 object VerilogGenerator extends App {
   (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
     new Top())))
-}
+}

lab2/src/main/scala/board/z710/Top.scala

@@ -83,6 +83,11 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
         cpu.io.memory_bundle <> mem.io.bundle
       }
     }
+
+    when (uart.io.bundle.write_enable) {
+      val the_char = cpu.io.memory_bundle.write_data(7, 0)
+      printf(cf"${the_char.asUInt}%c")
+    }
   }
 
   // LED, blinks every second

lab2/src/main/scala/board/z710v1.3/Top.scala

@@ -95,6 +95,11 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
       rom_loader.io.bundle.read_data := 0.U
       cpu.io.memory_bundle <> mem.io.bundle
     }
+
+    when (uart.io.bundle.write_enable) {
+      val the_char = cpu.io.memory_bundle.write_data(7, 0)
+      printf(cf"${the_char.asUInt}%c")
+    }
   }
 
   // LED, blinks every second