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fixed problems in Vivado 2020 of reset input from button

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PurplePower
2024-11-18 17:02:42 +08:00
parent 3e3c8ba6c0
commit ad0aaa823f
3 changed files with 32 additions and 31 deletions
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7
lab1/vivado/z710v1.3/generate_bitstream.tcl
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@@ -19,6 +19,8 @@ set project_name "rv-z710v1.3-20"
open_project $project_dir/$project_name.xpr open_project $project_dir/$project_name.xpr
update_module_reference design_1_Top_0_0
while 1 { while 1 {
if { [catch {launch_runs synth_1 -jobs 4 } ] } { if { [catch {launch_runs synth_1 -jobs 4 } ] } {
regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
@@ -59,8 +61,3 @@ while 1 {
wait_on_run impl_1 wait_on_run impl_1
# export hardware platform to Vitis
set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]
write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa

48
lab1/vivado/z710v1.3/rv-z710v1.3-20.tcl
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@@ -3,7 +3,7 @@
# #
# rv-z710v1.3-20.tcl: Tcl script for re-creating project 'rv-z710v1.3-20' # rv-z710v1.3-20.tcl: Tcl script for re-creating project 'rv-z710v1.3-20'
# #
# Generated by Vivado on Mon Nov 18 09:57:15 +0800 2024 # Generated by Vivado on Mon Nov 18 16:57:58 +0800 2024
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
# #
# This file contains the Vivado Tcl commands for re-creating the project to the state* # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -132,9 +132,9 @@ set files [list \
add_files -norecurse -fileset $obj $files add_files -norecurse -fileset $obj $files
# Import local files from the original project # Import local files from the original project
# set files [list \ set files [list \
# [file normalize "${origin_dir}/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ [file normalize "${origin_dir}/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\
# ] ]
set imported_files [import_files -fileset sources_1 $files] set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files # Set 'sources_1' fileset file properties for remote files
@@ -194,10 +194,10 @@ set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added # Adding sources referenced in BDs, if not already added
if { [get_files Top.v] == "" } { if { [get_files Top.v] == "" } {
import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710v1.3/Top.v" import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/Top.v
} }
if { [get_files clock_control.v] == "" } { if { [get_files clock_control.v] == "" } {
import_files -quiet -fileset sources_1 "${origin_dir}/../..//verilog/z710v1.3/clock_control.v" import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/clock_control.v
} }
@@ -304,15 +304,12 @@ proc cr_bd_design_1 { parentCell } {
# Create interface ports # Create interface ports
# Create ports # Create ports
set UART0_RX_0 [ create_bd_port -dir I UART0_RX_0 ] set UART0_RX_0 [ create_bd_port -dir I -type data UART0_RX_0 ]
set UART0_TX_0 [ create_bd_port -dir O -type data UART0_TX_0 ] set UART0_TX_0 [ create_bd_port -dir O UART0_TX_0 ]
set clk_enalbe [ create_bd_port -dir I -type ce clk_enalbe ] set clk_enable [ create_bd_port -dir I -type ce clk_enable ]
set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ]
set io_led [ create_bd_port -dir O io_led ] set io_led [ create_bd_port -dir O io_led ]
set io_reset [ create_bd_port -dir I -type rst io_reset ] set io_reset [ create_bd_port -dir I io_reset ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_HIGH} \
] $io_reset
# Create instance: Top_0, and set properties # Create instance: Top_0, and set properties
set block_name Top set block_name Top
@@ -325,6 +322,10 @@ proc cr_bd_design_1 { parentCell } {
return 1 return 1
} }
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] [get_bd_pins /Top_0/reset]
# Create instance: clock_control_0, and set properties # Create instance: clock_control_0, and set properties
set block_name clock_control set block_name clock_control
set block_cell_name clock_control_0 set block_cell_name clock_control_0
@@ -348,7 +349,7 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_net -net Top_0_io_led [get_bd_ports io_led] [get_bd_pins Top_0/io_led] connect_bd_net -net Top_0_io_led [get_bd_ports io_led] [get_bd_pins Top_0/io_led]
connect_bd_net -net Top_0_io_tx [get_bd_ports UART0_TX_0] [get_bd_pins Top_0/io_tx] connect_bd_net -net Top_0_io_tx [get_bd_ports UART0_TX_0] [get_bd_pins Top_0/io_tx]
connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins Top_0/io_rx] connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins Top_0/io_rx]
connect_bd_net -net clk_enalbe_1 [get_bd_ports clk_enalbe] [get_bd_pins clock_control_0/clk_enalbe] connect_bd_net -net clk_enable_1 [get_bd_ports clk_enable] [get_bd_pins clock_control_0/clk_enable]
connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out] connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out]
connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in] connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in]
connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins util_vector_logic_0/Op1] connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins util_vector_logic_0/Op1]
@@ -360,27 +361,27 @@ proc cr_bd_design_1 { parentCell } {
regenerate_bd_layout -layout_string { regenerate_bd_layout -layout_string {
"ActiveEmotionalView":"Default View", "ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0", "Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-343,-119", "Default View_TopLeft":"-220,-106",
"ExpandedHierarchyInLayout":"", "ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
# -string -flagsOSRD # -string -flagsOSRD
preplace port io_reset -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
preplace port io_clock -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD preplace port io_clock -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
preplace port clk_enalbe -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD preplace port clk_enable -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
preplace port UART0_RX_0 -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD preplace port UART0_RX_0 -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
preplace port UART0_TX_0 -pg 1 -lvl 3 -x 540 -y 170 -defaultsOSRD preplace port UART0_TX_0 -pg 1 -lvl 3 -x 540 -y 170 -defaultsOSRD
preplace port io_led -pg 1 -lvl 3 -x 540 -y 190 -defaultsOSRD preplace port io_led -pg 1 -lvl 3 -x 540 -y 190 -defaultsOSRD
preplace port io_reset -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
preplace inst Top_0 -pg 1 -lvl 2 -x 420 -y 180 -defaultsOSRD preplace inst Top_0 -pg 1 -lvl 2 -x 420 -y 180 -defaultsOSRD
preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 170 -y 180 -defaultsOSRD
preplace inst clock_control_0 -pg 1 -lvl 1 -x 170 -y 70 -defaultsOSRD preplace inst clock_control_0 -pg 1 -lvl 1 -x 170 -y 70 -defaultsOSRD
preplace netloc io_reset_1 1 0 1 NJ 180 preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 170 -y 180 -defaultsOSRD
preplace netloc util_vector_logic_0_Res 1 1 1 NJ 180
preplace netloc io_clock_1 1 0 1 NJ 60 preplace netloc io_clock_1 1 0 1 NJ 60
preplace netloc clk_enalbe_1 1 0 1 NJ 80
preplace netloc clock_control_0_clk_out 1 1 1 320 70n preplace netloc clock_control_0_clk_out 1 1 1 320 70n
preplace netloc UART0_RX_0_1 1 0 2 NJ 240 320J preplace netloc UART0_RX_0_1 1 0 2 NJ 240 320J
preplace netloc Top_0_io_tx 1 2 1 NJ 170 preplace netloc Top_0_io_tx 1 2 1 NJ 170
preplace netloc clk_enable_1 1 0 1 NJ 80
preplace netloc Top_0_io_led 1 2 1 NJ 190 preplace netloc Top_0_io_led 1 2 1 NJ 190
preplace netloc io_reset_1 1 0 1 NJ 180
preplace netloc util_vector_logic_0_Res 1 1 1 NJ 180
levelinfo -pg 1 0 170 420 540 levelinfo -pg 1 0 170 420 540
pagesize -pg 1 -db -bbox -sgen -140 0 680 260 pagesize -pg 1 -db -bbox -sgen -140 0 680 260
" "
@@ -394,12 +395,11 @@ pagesize -pg 1 -db -bbox -sgen -140 0 680 260
close_bd_design $design_name close_bd_design $design_name
} }
# End of cr_bd_design_1() # End of cr_bd_design_1()
cr_bd_design_1 "" cr_bd_design_1 ""
set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
# create HDL wrapper # make wrapper for design_1.db
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
add_files -norecurse -fileset sources_1 $wrapper_path add_files -norecurse -fileset sources_1 $wrapper_path
@@ -423,6 +423,7 @@ if { $obj != "" } {
} }
set obj [get_runs synth_1] set obj [get_runs synth_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xc7z010clg400-1" -objects $obj set_property -name "part" -value "xc7z010clg400-1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
@@ -637,6 +638,7 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj
} }
set obj [get_runs impl_1] set obj [get_runs impl_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xc7z010clg400-1" -objects $obj set_property -name "part" -value "xc7z010clg400-1" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj

8
lab1/vivado/z710v1.3/z710v1.3.xdc
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@@ -15,10 +15,12 @@ set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0
#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2]; #set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2];
# switches # switches
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enalbe]; # PL_SW1 set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enable]; # PL_SW1
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_SW2
# do NOT assign reset to ANY BUTTON in Vivado 2020, its Utility Vector Logic Not cause unstable TX output
# while this isn't present in Vivado 2022
# buttons
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_KEY0
# UART ports # UART ports