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update the Top.scala for Z710

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This commit is contained in:
PurplePower
2024-11-18 22:35:36 +08:00
parent ddb70fa967
commit 93ac859c8f
1 changed files with 10 additions and 5 deletions
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15
lab1/src/main/scala/board/z710/Top.scala
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@@ -28,11 +28,16 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
val led = Output(Bool()) // z710 has few LEDs, use one for running indicator val led = Output(Bool()) // z710 has few LEDs, use one for running indicator
}) })
// original ref clock is 125MHz, divided in clock_control.v by 5 to avoid total negative slack too large
val clock_freq = 25_000_000
val mem = Module(new Memory(Parameters.MemorySizeInWords)) val mem = Module(new Memory(Parameters.MemorySizeInWords))
// val hdmi_display = Module(new HDMIDisplay) // val hdmi_display = Module(new HDMIDisplay)
// val display = Module(new CharacterDisplay) // val display = Module(new CharacterDisplay)
// val timer = Module(new Timer) // val timer = Module(new Timer)
val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error
val dummy = Module(new Dummy) val dummy = Module(new Dummy)
// display.io.bundle <> dummy.io.bundle // display.io.bundle <> dummy.io.bundle
@@ -53,7 +58,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
val CPU_clkdiv = RegInit(UInt(2.W),0.U) val CPU_clkdiv = RegInit(UInt(2.W),0.U)
val CPU_tick = Wire(Bool()) val CPU_tick = Wire(Bool())
val CPU_next = Wire(UInt(2.W)) val CPU_next = Wire(UInt(2.W))
CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U) CPU_next := Mux(CPU_clkdiv === 9.U, 0.U, CPU_clkdiv + 1.U)
CPU_tick := CPU_clkdiv === 0.U CPU_tick := CPU_clkdiv === 0.U
CPU_clkdiv := CPU_next CPU_clkdiv := CPU_next
@@ -90,14 +95,14 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
} }
// LED, blinks every second // LED, blinks every second
val clock_freq = 40_000_000.U
val led_count = RegInit(0.U(32.W)) val led_count = RegInit(0.U(32.W))
when (led_count >= clock_freq) { when (led_count >= clock_freq.U) {
led_count := 0.U led_count := 0.U
}.otherwise { }.otherwise {
led_count := led_count + 1.U led_count := led_count + 1.U
} }
io.led := (led_count >= (clock_freq >> 1)) io.led := (led_count >= (clock_freq.U >> 1))