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TOKISAKIX\21168
307
lab4/vivado/basys3/basys3.xdc
Normal file
307
lab4/vivado/basys3/basys3.xdc
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@@ -0,0 +1,307 @@
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||||
# Copyright 2021 Howard Lau
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
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||||
# http://www.apache.org/licenses/LICENSE-2.0
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||||
#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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## Clock signal
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set_property PACKAGE_PIN W5 [get_ports clock]
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set_property IOSTANDARD LVCMOS33 [get_ports clock]
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create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 5} [get_ports clock]
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## Switches
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set_property PACKAGE_PIN V17 [get_ports {io_switch[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[0]}]
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set_property PACKAGE_PIN V16 [get_ports {io_switch[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[1]}]
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set_property PACKAGE_PIN W16 [get_ports {io_switch[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[2]}]
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set_property PACKAGE_PIN W17 [get_ports {io_switch[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[3]}]
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set_property PACKAGE_PIN W15 [get_ports {io_switch[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[4]}]
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set_property PACKAGE_PIN V15 [get_ports {io_switch[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[5]}]
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set_property PACKAGE_PIN W14 [get_ports {io_switch[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[6]}]
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set_property PACKAGE_PIN W13 [get_ports {io_switch[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[7]}]
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set_property PACKAGE_PIN V2 [get_ports {io_switch[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[8]}]
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set_property PACKAGE_PIN T3 [get_ports {io_switch[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[9]}]
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set_property PACKAGE_PIN T2 [get_ports {io_switch[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[10]}]
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set_property PACKAGE_PIN R3 [get_ports {io_switch[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[11]}]
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set_property PACKAGE_PIN W2 [get_ports {io_switch[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[12]}]
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set_property PACKAGE_PIN U1 [get_ports {io_switch[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[13]}]
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set_property PACKAGE_PIN T1 [get_ports {io_switch[14]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[14]}]
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set_property PACKAGE_PIN R2 [get_ports {io_switch[15]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[15]}]
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## LEDs
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set_property PACKAGE_PIN U16 [get_ports {io_led[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[0]}]
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set_property PACKAGE_PIN E19 [get_ports {io_led[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[1]}]
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set_property PACKAGE_PIN U19 [get_ports {io_led[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[2]}]
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set_property PACKAGE_PIN V19 [get_ports {io_led[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[3]}]
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set_property PACKAGE_PIN W18 [get_ports {io_led[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[4]}]
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set_property PACKAGE_PIN U15 [get_ports {io_led[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[5]}]
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set_property PACKAGE_PIN U14 [get_ports {io_led[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[6]}]
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set_property PACKAGE_PIN V14 [get_ports {io_led[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[7]}]
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set_property PACKAGE_PIN V13 [get_ports {io_led[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[8]}]
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set_property PACKAGE_PIN V3 [get_ports {io_led[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[9]}]
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set_property PACKAGE_PIN W3 [get_ports {io_led[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[10]}]
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set_property PACKAGE_PIN U3 [get_ports {io_led[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[11]}]
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set_property PACKAGE_PIN P3 [get_ports {io_led[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[12]}]
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set_property PACKAGE_PIN N3 [get_ports {io_led[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[13]}]
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set_property PACKAGE_PIN P1 [get_ports {io_led[14]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[14]}]
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set_property PACKAGE_PIN L1 [get_ports {io_led[15]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_led[15]}]
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##7 segment display
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set_property PACKAGE_PIN U7 [get_ports io_segs[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[0]]
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set_property PACKAGE_PIN V5 [get_ports io_segs[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[1]]
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set_property PACKAGE_PIN U5 [get_ports io_segs[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[2]]
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set_property PACKAGE_PIN V8 [get_ports io_segs[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[3]]
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set_property PACKAGE_PIN U8 [get_ports io_segs[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[4]]
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set_property PACKAGE_PIN W6 [get_ports io_segs[5]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[5]]
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set_property PACKAGE_PIN W7 [get_ports io_segs[6]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[6]]
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set_property PACKAGE_PIN V7 [get_ports io_segs[7]]
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set_property IOSTANDARD LVCMOS33 [get_ports io_segs[7]]
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set_property PACKAGE_PIN U2 [get_ports {io_digit_mask[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[0]}]
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set_property PACKAGE_PIN U4 [get_ports {io_digit_mask[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[1]}]
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set_property PACKAGE_PIN V4 [get_ports {io_digit_mask[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[2]}]
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set_property PACKAGE_PIN W4 [get_ports {io_digit_mask[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[3]}]
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##Buttons
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set_property PACKAGE_PIN U18 [get_ports reset]
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set_property IOSTANDARD LVCMOS33 [get_ports reset]
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#set_property PACKAGE_PIN T18 [get_ports io_freqIncrease]
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#set_property IOSTANDARD LVCMOS33 [get_ports io_freqIncrease]
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#set_property PACKAGE_PIN W19 [get_ports io_widthIncrease]
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#set_property IOSTANDARD LVCMOS33 [get_ports io_widthIncrease]
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#set_property PACKAGE_PIN T17 [get_ports io_widthDecrease]
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#set_property IOSTANDARD LVCMOS33 [get_ports io_widthDecrease]
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#set_property PACKAGE_PIN U17 [get_ports io_freqDecrease]
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#set_property IOSTANDARD LVCMOS33 [get_ports io_freqDecrease]
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##Pmod Header JA
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##Sch name = JA1
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#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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##Sch name = JA2
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#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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##Sch name = JA3
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#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
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##Sch name = JA4
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#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
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##Sch name = JA7
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#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
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##Sch name = JA8
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#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
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##Sch name = JA9
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#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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##Sch name = JA10
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#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
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##Pmod Header JB
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##Sch name = JB1
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#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
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##Sch name = JB2
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#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
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##Sch name = JB3
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#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
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##Sch name = JB4
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#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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##Sch name = JB7
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#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
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##Sch name = JB8
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#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
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##Sch name = JB9
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#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
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##Sch name = JB10
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#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
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##Pmod Header JC
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##Sch name = JC1
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#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
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##Sch name = JC2
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#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
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##Sch name = JC3
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#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
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##Sch name = JC4
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#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
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##Sch name = JC7
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||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
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||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
set_property PACKAGE_PIN G19 [get_ports {io_rgb[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[8]}]
|
||||
set_property PACKAGE_PIN H19 [get_ports {io_rgb[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[9]}]
|
||||
set_property PACKAGE_PIN J19 [get_ports {io_rgb[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[10]}]
|
||||
set_property PACKAGE_PIN N19 [get_ports {io_rgb[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[11]}]
|
||||
set_property PACKAGE_PIN N18 [get_ports {io_rgb[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[0]}]
|
||||
set_property PACKAGE_PIN L18 [get_ports {io_rgb[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[1]}]
|
||||
set_property PACKAGE_PIN K18 [get_ports {io_rgb[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[2]}]
|
||||
set_property PACKAGE_PIN J18 [get_ports {io_rgb[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[3]}]
|
||||
set_property PACKAGE_PIN J17 [get_ports {io_rgb[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[4]}]
|
||||
set_property PACKAGE_PIN H17 [get_ports {io_rgb[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[5]}]
|
||||
set_property PACKAGE_PIN G17 [get_ports {io_rgb[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[6]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {io_rgb[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[7]}]
|
||||
set_property PACKAGE_PIN P19 [get_ports io_hsync]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_hsync]
|
||||
set_property PACKAGE_PIN R19 [get_ports io_vsync]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
set_property PACKAGE_PIN B18 [get_ports io_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_rx]
|
||||
set_property PACKAGE_PIN A18 [get_ports io_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_tx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
17
lab4/vivado/basys3/generate_and_program.tcl
Normal file
17
lab4/vivado/basys3/generate_and_program.tcl
Normal file
@@ -0,0 +1,17 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
source generate_bitstream.tcl
|
||||
source program_device.tcl
|
||||
55
lab4/vivado/basys3/generate_bitstream.tcl
Normal file
55
lab4/vivado/basys3/generate_bitstream.tcl
Normal file
@@ -0,0 +1,55 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
source open_project.tcl
|
||||
|
||||
while 1 {
|
||||
if { [catch {launch_runs synth_1 -jobs 4 } ] } {
|
||||
regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
|
||||
if { [string equal $code "12-978"] } {
|
||||
puts "Already generated and up-to-date"
|
||||
break
|
||||
} elseif { [string equal $code "17-69"] } {
|
||||
puts "Out of date, reset runs"
|
||||
reset_runs synth_1
|
||||
continue
|
||||
} else {
|
||||
puts "UNKNOWN ERROR!!! $errorInfo"
|
||||
exit
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
wait_on_run synth_1
|
||||
|
||||
while 1 {
|
||||
if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
|
||||
regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
|
||||
if { [string equal $code "12-978"] } {
|
||||
puts "Already generated and up-to-date"
|
||||
break
|
||||
} elseif { [string equal $code "12-1088"] } {
|
||||
puts "Out of date, reset runs"
|
||||
reset_runs impl_1
|
||||
continue
|
||||
} else {
|
||||
puts "UNKNOWN ERROR!!! $errorInfo"
|
||||
exit
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
wait_on_run impl_1
|
||||
39
lab4/vivado/basys3/open_project.tcl
Normal file
39
lab4/vivado/basys3/open_project.tcl
Normal file
@@ -0,0 +1,39 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
|
||||
# set variables
|
||||
set project_dir riscv-basys3
|
||||
set project_name riscv-basys3
|
||||
set part xc7a35tcpg236-1
|
||||
set sources {../../verilog/basys3/Top.v}
|
||||
set test_sources {../../verilog/basys3/test.v}
|
||||
|
||||
# open the project. will create one if it doesn't exist
|
||||
if {[file exist $project_dir]} {
|
||||
# check that it's a directory
|
||||
if {! [file isdirectory $project_dir]} {
|
||||
puts "$project_dir exists, but it's a file"
|
||||
}
|
||||
open_project $project_dir/$project_name.xpr -part $part
|
||||
} else {
|
||||
create_project $project_name $project_dir -part $part
|
||||
}
|
||||
|
||||
add_files -norecurse $sources
|
||||
update_compile_order -fileset sources_1
|
||||
add_files -fileset constrs_1 -norecurse basys3.xdc
|
||||
add_files -fileset sim_1 -norecurse $test_sources
|
||||
update_compile_order -fileset sim_1
|
||||
24
lab4/vivado/basys3/program_device.tcl
Normal file
24
lab4/vivado/basys3/program_device.tcl
Normal file
@@ -0,0 +1,24 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
open_hw_manager
|
||||
connect_hw_server -allow_non_jtag
|
||||
open_hw_target
|
||||
current_hw_device [get_hw_devices xc7a35t_0]
|
||||
refresh_hw_server [current_hw_server]
|
||||
open_hw_target [lindex [get_hw_targets] 0]
|
||||
set_property PROGRAM.FILE {./riscv-basys3/riscv-basys3.runs/impl_1/Top.bit} [get_hw_devices xc7a35t_0]
|
||||
program_hw_devices [get_hw_devices xc7a35t_0]
|
||||
close_hw_target
|
||||
4
lab4/vivado/basys3/run.ps1
Normal file
4
lab4/vivado/basys3/run.ps1
Normal file
@@ -0,0 +1,4 @@
|
||||
cd ..
|
||||
sbt run
|
||||
cd vivado
|
||||
C:\Xilinx\Vivado\2020.1\bin\vivado -mode batch -source .\generate_and_program.tcl
|
||||
24
lab4/vivado/basys3/run_simulation.tcl
Normal file
24
lab4/vivado/basys3/run_simulation.tcl
Normal file
@@ -0,0 +1,24 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
source open_project.tcl
|
||||
|
||||
launch_simulation
|
||||
restart
|
||||
open_vcd
|
||||
log_wave -recursive [get_object /test/top/cpu/*]
|
||||
log_vcd [get_object /test/top/cpu/*]
|
||||
run 1000ns
|
||||
close_vcd
|
||||
close_sim
|
||||
17
lab4/vivado/pynq/generate_and_program.tcl
Normal file
17
lab4/vivado/pynq/generate_and_program.tcl
Normal file
@@ -0,0 +1,17 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
source generate_bitstream.tcl
|
||||
source program_device.tcl
|
||||
57
lab4/vivado/pynq/generate_bitstream.tcl
Normal file
57
lab4/vivado/pynq/generate_bitstream.tcl
Normal file
@@ -0,0 +1,57 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
source open_project.tcl
|
||||
set_param general.maxThreads 16
|
||||
update_module_reference design_1_Top_0_0
|
||||
|
||||
while 1 {
|
||||
if { [catch {launch_runs synth_1 -jobs 16 } ] } {
|
||||
regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
|
||||
if { [string equal $code "12-978"] } {
|
||||
puts "Already generated and up-to-date"
|
||||
break
|
||||
} elseif { [string equal $code "17-69"] } {
|
||||
puts "Out of date, reset runs"
|
||||
reset_runs synth_1
|
||||
continue
|
||||
} else {
|
||||
puts "UNKNOWN ERROR!!! $errorInfo"
|
||||
exit
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
wait_on_run synth_1
|
||||
|
||||
while 1 {
|
||||
if { [catch {launch_runs impl_1 -jobs 16 -to_step write_bitstream } ] } {
|
||||
regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
|
||||
if { [string equal $code "12-978"] } {
|
||||
puts "Already generated and up-to-date"
|
||||
break
|
||||
} elseif { [string equal $code "12-1088"] } {
|
||||
puts "Out of date, reset runs"
|
||||
reset_runs impl_1
|
||||
continue
|
||||
} else {
|
||||
puts "UNKNOWN ERROR!!! $errorInfo"
|
||||
exit
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
wait_on_run impl_1
|
||||
29
lab4/vivado/pynq/open_project.tcl
Normal file
29
lab4/vivado/pynq/open_project.tcl
Normal file
@@ -0,0 +1,29 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
set project_dir riscv-pynq
|
||||
set project_name riscv-pynq
|
||||
set part xc7z020clg400-1
|
||||
|
||||
# open the project. will create one if it doesn't exist
|
||||
if {[file exist $project_dir]} {
|
||||
# check that it's a directory
|
||||
if {! [file isdirectory $project_dir]} {
|
||||
puts "$project_dir exists, but it's a file"
|
||||
}
|
||||
open_project $project_dir/$project_name.xpr -part $part
|
||||
} else {
|
||||
source riscv-pynq.tcl
|
||||
}
|
||||
22
lab4/vivado/pynq/program_device.tcl
Normal file
22
lab4/vivado/pynq/program_device.tcl
Normal file
@@ -0,0 +1,22 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# Only tested on Vivado 2020.1 on Windows 10
|
||||
open_hw_manager
|
||||
connect_hw_server -allow_non_jtag
|
||||
refresh_hw_server [current_hw_server]
|
||||
open_hw_target [lindex [get_hw_targets] 0]
|
||||
set_property PROGRAM.FILE {riscv-pynq/riscv-pynq.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z020_1]
|
||||
program_hw_devices [get_hw_devices xc7z020_1]
|
||||
close_hw_target
|
||||
189
lab4/vivado/pynq/pynq.xdc
Normal file
189
lab4/vivado/pynq/pynq.xdc
Normal file
@@ -0,0 +1,189 @@
|
||||
## This file is a general .xdc for the PYNQ-Z1 board Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal 125 MHz
|
||||
|
||||
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clock }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
|
||||
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clock }];
|
||||
|
||||
##Switches
|
||||
|
||||
set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { io_debug_step }]; #IO_L7N_T1_AD2N_35 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1]
|
||||
|
||||
##RGB LEDs
|
||||
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7N_35 Sch=led4_b
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=led4_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led4_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=led5_b
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=led5_g
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=led5_r
|
||||
|
||||
##LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { io_led[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { io_led[1] }]; #IO_L6P_T0_34 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { io_led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_led[3] }]; #IO_L23P_T3_35 Sch=led[3]
|
||||
|
||||
##Buttons
|
||||
|
||||
set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L4P_T0_35 Sch=btn[0]
|
||||
set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { io_debug_clk }]; #IO_L4N_T0_35 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3]
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { io_rx }]; #IO_L17P_T2_34 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { io_tx }]; #IO_L17N_T2_34 Sch=ja_n[1]
|
||||
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { io_rx }]; #IO_L7P_T1_34 Sch=ja_p[2]
|
||||
set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { io_tx }]; #IO_L7N_T1_34 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
|
||||
|
||||
##Audio Out
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=aud_sd
|
||||
|
||||
##Mic input
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_L6N_T0_VREF_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L16N_T2_35 Sch=m_data
|
||||
|
||||
##ChipKit Single Ended Analog Inputs
|
||||
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
|
||||
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
|
||||
|
||||
##ChipKit Digital I/O Low
|
||||
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L5P_T0_34 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L2N_T0_34 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L3N_T0_DQS_34 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L10P_T1_34 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L5N_T0_34 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L19P_T3_34 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L9N_T1_DQS_34 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L21P_T3_DQS_34 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L21N_T3_DQS_34 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L9P_T1_DQS_34 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L19N_T3_VREF_34 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L23N_T3_34 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L23P_T3_34 Sch=ck_io[13]
|
||||
|
||||
##ChipKit Digital I/O On Outer Analog Header
|
||||
##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_L18N_T2_13 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L20P_T3_13 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L18P_T2_13 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L21P_T3_DQS_13 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L19P_T3_13 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L12N_T1_MRCC_13 Sch=ck_a[5]
|
||||
|
||||
##ChipKit Digital I/O On Inner Analog Header
|
||||
##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
|
||||
##ChipKit Digital I/O High
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_VREF_13 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L6N_T0_VREF_13 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L22P_T3_13 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_L11P_T1_SRCC_13 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_L11N_T1_SRCC_13 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L17N_T2_13 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L15P_T2_DQS_13 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L21N_T3_DQS_13 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L16P_T2_13 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L22N_T3_13 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L13N_T2_MRCC_13 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L13P_T2_MRCC_13 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L15N_T2_DQS_13 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L14N_T2_SRCC_13 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L16N_T2_13 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L14P_T2_SRCC_13 Sch=ck_io[41]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[42] }]; #IO_L20N_T3_13 Sch=ck_ioa
|
||||
|
||||
## ChipKit SPI
|
||||
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
|
||||
|
||||
##HDMI Rx
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec
|
||||
set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n
|
||||
set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p
|
||||
set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0]
|
||||
set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0]
|
||||
set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1]
|
||||
set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1]
|
||||
set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2]
|
||||
set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2]
|
||||
set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { io_debug_hdmi_hpdn }]; #IO_25_34 Sch=hdmi_rx_hpd
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda
|
||||
|
||||
##HDMI Tx
|
||||
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec
|
||||
set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=hdmi_tx_clk_n
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=hdmi_tx_clk_p
|
||||
set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=hdmi_tx_d_n[0]
|
||||
set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=hdmi_tx_d_p[0]
|
||||
set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=hdmi_tx_d_n[1]
|
||||
set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=hdmi_tx_d_p[1]
|
||||
set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=hdmi_tx_d_n[2]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { io_hdmi_data_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=hdmi_tx_d_p[2]
|
||||
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { io_hdmi_hpdn }]; #IO_0_34 Sch=hdmi_tx_hpdn
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=hdmi_tx_sda
|
||||
|
||||
##Crypto SDA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda
|
||||
1602
lab4/vivado/pynq/riscv-pynq.tcl
Normal file
1602
lab4/vivado/pynq/riscv-pynq.tcl
Normal file
File diff suppressed because it is too large
Load Diff
4
lab4/vivado/pynq/run.ps1
Normal file
4
lab4/vivado/pynq/run.ps1
Normal file
@@ -0,0 +1,4 @@
|
||||
cd ..
|
||||
sbt run
|
||||
cd vivado
|
||||
C:\Xilinx\Vivado\2020.1\bin\vivado -mode batch -source .\generate_and_program.tcl
|
||||
28
lab4/vivado/pynq/run_simulation.tcl
Normal file
28
lab4/vivado/pynq/run_simulation.tcl
Normal file
@@ -0,0 +1,28 @@
|
||||
# Copyright 2021 Howard Lau
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
source open_project.tcl
|
||||
|
||||
launch_simulation
|
||||
restart
|
||||
open_vcd
|
||||
#log_wave -recursive [get_object /test/top/hdmi_display/*]
|
||||
#log_vcd [get_object /test/top/hdmi_display/*]
|
||||
#log_wave -recursive [get_object /test/top/*]
|
||||
#log_vcd [get_object /test/top/*]
|
||||
log_wave -recursive [get_object /test/top/hdmi_display/serdesBlue/osr10/*]
|
||||
log_vcd [get_object /test/top/hdmi_display/serdesBlue/osr10/*]
|
||||
run 1000000ns
|
||||
close_vcd
|
||||
close_sim
|
||||
Reference in New Issue
Block a user