init repo

lab4/src/main/scala/board/basys3/BCD2Segments.scala

@@ -0,0 +1,54 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class BCD2Segments extends Module {
+  val io = IO(new Bundle {
+    val bcd = Input(UInt(4.W))
+    val segs = Output(UInt(8.W))
+  })
+
+  val bcd = io.bcd
+  val segs = Wire(UInt(8.W))
+
+  segs := MuxLookup(
+    bcd,
+    0xFF.U,
+    IndexedSeq(
+      0.U -> "b10000001".U,
+      1.U -> "b11001111".U,
+      2.U -> "b10010010".U,
+      3.U -> "b10000110".U,
+      4.U -> "b11001100".U,
+      5.U -> "b10100100".U,
+      6.U -> "b10100000".U,
+      7.U -> "b10001111".U,
+      8.U -> "b10000000".U,
+      9.U -> "b10000100".U,
+      10.U -> "b00001000".U,
+      11.U -> "b01100000".U,
+      12.U -> "b00110001".U,
+      13.U -> "b01000010".U,
+      14.U -> "b00110000".U,
+      15.U -> "b00111000".U,
+    )
+  )
+
+  io.segs := segs
+}
+

lab4/src/main/scala/board/basys3/OnboardDigitDisplay.scala

@@ -0,0 +1,32 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+
+class OnboardDigitDisplay extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Output(UInt(4.W))
+  })
+
+  val counter = RegInit(UInt(16.W), 0.U)
+  val digit_mask = RegInit(UInt(4.W), "b0111".U)
+
+  counter := counter + 1.U
+  when(counter === 0.U) {
+    digit_mask := (digit_mask << 1.U).asUInt + digit_mask(3)
+  }
+  io.digit_mask := digit_mask
+}

lab4/src/main/scala/board/basys3/SYSULogo.scala

@@ -0,0 +1,34 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class SYSULogo extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Input(UInt(4.W))
+    val segs = Output(UInt(8.W))
+  })
+
+  io.segs := MuxLookup(
+    io.digit_mask,
+    "b00100100".U, // "b0111".U, "b1101".U -> S
+    IndexedSeq(
+      "b1011".U -> "b01000100".U, // Y
+      "b1110".U -> "b01000001".U, // U
+    )
+  )
+}

lab4/src/main/scala/board/basys3/SegmentMux.scala

@@ -0,0 +1,42 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class SegmentMux extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Input(UInt(4.W))
+    val numbers = Input(UInt(16.W))
+    val segs = Output(UInt(8.W))
+  })
+
+
+  val digit = RegInit(UInt(4.W), 0.U)
+  val bcd2segs = Module(new BCD2Segments)
+
+  bcd2segs.io.bcd := digit
+  io.segs := bcd2segs.io.segs
+  digit := MuxLookup(
+    io.digit_mask,
+    io.numbers(3, 0), // "b1110".U
+    IndexedSeq(
+      "b1101".U -> io.numbers(7, 4),
+      "b1011".U -> io.numbers(11, 8),
+      "b0111".U -> io.numbers(15, 12)
+    )
+  )
+}

lab4/src/main/scala/board/basys3/Top.scala

@@ -0,0 +1,143 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.experimental.ChiselEnum
+import chisel3.util._
+import riscv._
+import peripheral.{CharacterDisplay, DummySlave, InstructionROM, Memory, ROMLoader, Timer, Uart, VGADisplay}
+import bus.{BusArbiter, BusSwitch}
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import riscv.core.CPU
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, Finished = Value
+}
+
+class Top extends Module {
+  val binaryFilename = "tetris.asmbin"
+  val io = IO(new Bundle {
+    val switch = Input(UInt(16.W))
+
+    val segs = Output(UInt(8.W))
+    val digit_mask = Output(UInt(4.W))
+
+    val hsync = Output(Bool())
+    val vsync = Output(Bool())
+    val rgb = Output(UInt(12.W))
+    val led = Output(UInt(16.W))
+
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val uart = Module(new Uart(100000000, 115200))
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  val vga_display = Module(new VGADisplay)
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+  val display = Module(new CharacterDisplay)
+  bus_switch.io.slaves(1) <> display.io.channels
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+  io.hsync := vga_display.io.hsync
+  io.vsync := vga_display.io.vsync
+
+  display.io.x := vga_display.io.x
+  display.io.y := vga_display.io.y
+  display.io.video_on := vga_display.io.video_on
+
+  io.rgb := display.io.rgb
+
+  mem.io.debug_read_address := io.switch(15, 1).asUInt << 2
+  io.led := Mux(
+    io.switch(0),
+    mem.io.debug_read_data(31, 16).asUInt,
+    mem.io.debug_read_data(15, 0).asUInt,
+  )
+
+  val onboard_display = Module(new OnboardDigitDisplay)
+  io.digit_mask := onboard_display.io.digit_mask
+
+  val sysu_logo = Module(new SYSULogo)
+  sysu_logo.io.digit_mask := io.digit_mask
+
+  val seg_mux = Module(new SegmentMux)
+  seg_mux.io.digit_mask := io.digit_mask
+  seg_mux.io.numbers := io.led
+
+  io.segs := MuxLookup(
+    io.switch,
+    seg_mux.io.segs,
+    IndexedSeq(
+      0.U -> sysu_logo.io.segs
+    )
+  )
+}
+
+object VerilogGenerator extends App {
+  (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/basys3"), Seq(ChiselGeneratorAnnotation(() => new Top)))
+}