mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
init repo
This commit is contained in:
TOKISAKIX\21168
35
lab3/verilog/basys3/test.v
Normal file
35
lab3/verilog/basys3/test.v
Normal file
@@ -0,0 +1,35 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/12/17 16:31:05
|
||||
// Design Name:
|
||||
// Module Name: test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module test();
|
||||
reg clock;
|
||||
reg reset;
|
||||
initial begin
|
||||
clock = 0;
|
||||
forever #1 clock = ~clock;
|
||||
end
|
||||
initial begin
|
||||
reset = 1;
|
||||
#2 reset = 0;
|
||||
end
|
||||
Top top(clock, reset);
|
||||
endmodule
|
||||
221
lab3/verilog/pynq/TMDS_PLLVR.v
Normal file
221
lab3/verilog/pynq/TMDS_PLLVR.v
Normal file
@@ -0,0 +1,221 @@
|
||||
|
||||
// file: TMDS_PLLVR.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// __clkout__250.00000______0.000______50.0______200.536____237.727
|
||||
// _clkoutd__100.00000______0.000______50.0______226.965____237.727
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________25.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "TMDS_PLLVR,clk_wiz_v6_0_5_0_0,{component_name=TMDS_PLLVR,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=true}" *)
|
||||
|
||||
module TMDS_PLLVR
|
||||
(
|
||||
// Clock out ports
|
||||
output clkout,
|
||||
output clkoutd,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output lock,
|
||||
// Clock in ports
|
||||
input clkin
|
||||
);
|
||||
|
||||
TMDS_PLLVR_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clkout(clkout),
|
||||
.clkoutd(clkoutd),
|
||||
// Status and control signals
|
||||
.reset(reset),
|
||||
.lock(lock),
|
||||
// Clock in ports
|
||||
.clk_in1(clkin)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module TMDS_PLLVR_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clkout,
|
||||
output clkoutd,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output lock,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_TMDS_PLLVR;
|
||||
wire clk_in2_TMDS_PLLVR;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_TMDS_PLLVR),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clkout_TMDS_PLLVR;
|
||||
wire clkoutd_TMDS_PLLVR;
|
||||
wire clk_out3_TMDS_PLLVR;
|
||||
wire clk_out4_TMDS_PLLVR;
|
||||
wire clk_out5_TMDS_PLLVR;
|
||||
wire clk_out6_TMDS_PLLVR;
|
||||
wire clk_out7_TMDS_PLLVR;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire lock_int;
|
||||
wire clkfbout_TMDS_PLLVR;
|
||||
wire clkfbout_buf_TMDS_PLLVR;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
wire reset_high;
|
||||
|
||||
PLLE2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (40),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (4),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (10),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (40.000))
|
||||
plle2_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_TMDS_PLLVR),
|
||||
.CLKOUT0 (clkout_TMDS_PLLVR),
|
||||
.CLKOUT1 (clkoutd_TMDS_PLLVR),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_TMDS_PLLVR),
|
||||
.CLKIN1 (clk_in1_TMDS_PLLVR),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Other control and status signals
|
||||
.LOCKED (lock_int),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (reset_high));
|
||||
assign reset_high = reset;
|
||||
|
||||
assign lock = lock_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_TMDS_PLLVR),
|
||||
.I (clkfbout_TMDS_PLLVR));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clkout),
|
||||
.I (clkout_TMDS_PLLVR));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clkoutd),
|
||||
.I (clkoutd_TMDS_PLLVR));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
35
lab3/verilog/pynq/test.v
Normal file
35
lab3/verilog/pynq/test.v
Normal file
@@ -0,0 +1,35 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/12/17 16:31:05
|
||||
// Design Name:
|
||||
// Module Name: test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module test();
|
||||
reg clock;
|
||||
reg reset;
|
||||
initial begin
|
||||
clock = 0;
|
||||
forever #1 clock = ~clock;
|
||||
end
|
||||
initial begin
|
||||
reset = 1;
|
||||
#2 reset = 0;
|
||||
end
|
||||
Top top(clock, reset);
|
||||
endmodule
|
||||
251
lab3/verilog/verilator/sim_main.cpp
Normal file
251
lab3/verilog/verilator/sim_main.cpp
Normal file
@@ -0,0 +1,251 @@
|
||||
#include <verilated.h>
|
||||
#include <verilated_vcd_c.h>
|
||||
|
||||
#include <algorithm>
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
|
||||
#include "VTop.h" // From Verilating "top.v"
|
||||
|
||||
|
||||
class Memory {
|
||||
std::vector<uint32_t> memory;
|
||||
|
||||
public:
|
||||
Memory(size_t size) : memory(size, 0) {}
|
||||
|
||||
uint32_t read(size_t address) {
|
||||
address = address / 4;
|
||||
if (address >= memory.size()) {
|
||||
// printf("invalid read address 0x%08x\n", address * 4);
|
||||
return 0;
|
||||
}
|
||||
return memory[address];
|
||||
}
|
||||
|
||||
uint32_t readInst(size_t address) {
|
||||
address = address / 4;
|
||||
if (address >= memory.size()) {
|
||||
// printf("invalid read Inst address 0x%08x\n", address * 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return memory[address];
|
||||
}
|
||||
|
||||
void write(size_t address, uint32_t value, bool write_strobe[4]) {
|
||||
address = address / 4;
|
||||
uint32_t write_mask = 0;
|
||||
if (write_strobe[0]) write_mask |= 0x000000FF;
|
||||
if (write_strobe[1]) write_mask |= 0x0000FF00;
|
||||
if (write_strobe[2]) write_mask |= 0x00FF0000;
|
||||
if (write_strobe[3]) write_mask |= 0xFF000000;
|
||||
if (address >= memory.size()) {
|
||||
// printf("invalid write address 0x%08x\n", address * 4);
|
||||
return;
|
||||
}
|
||||
memory[address] = (memory[address] & ~write_mask) | (value & write_mask);
|
||||
}
|
||||
|
||||
void load_binary(std::string const& filename, size_t load_address = 0x1000) {
|
||||
std::ifstream file(filename, std::ios::binary);
|
||||
if (!file) {
|
||||
throw std::runtime_error("Could not open file " + filename);
|
||||
}
|
||||
file.seekg(0, std::ios::end);
|
||||
size_t size = file.tellg();
|
||||
if (load_address + size > memory.size() * 4) {
|
||||
throw std::runtime_error("File " + filename + " is too large (File is " +
|
||||
std::to_string(size) + " bytes. Memory is " +
|
||||
std::to_string(memory.size() * 4 - load_address) + " bytes.)");
|
||||
}
|
||||
file.seekg(0, std::ios::beg);
|
||||
for (int i = 0; i < size / 4; ++i) {
|
||||
file.read(reinterpret_cast<char*>(&memory[i + load_address / 4]),
|
||||
sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
class VCDTracer {
|
||||
VerilatedVcdC* tfp = nullptr;
|
||||
|
||||
public:
|
||||
void enable(std::string const& filename, VTop& top) {
|
||||
Verilated::traceEverOn(true);
|
||||
tfp = new VerilatedVcdC;
|
||||
top.trace(tfp, 99);
|
||||
tfp->open(filename.c_str());
|
||||
tfp->set_time_resolution("1ps");
|
||||
tfp->set_time_unit("1ns");
|
||||
if (!tfp->isOpen()) {
|
||||
throw std::runtime_error("Failed to open VCD dump file " + filename);
|
||||
}
|
||||
}
|
||||
|
||||
void dump(vluint64_t time) {
|
||||
if (tfp) {
|
||||
tfp->dump(time);
|
||||
}
|
||||
}
|
||||
|
||||
~VCDTracer() {
|
||||
if (tfp) {
|
||||
tfp->close();
|
||||
delete tfp;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
uint32_t parse_number(std::string const& str) {
|
||||
if (str.size() > 2) {
|
||||
auto&& prefix = str.substr(0, 2);
|
||||
if (prefix == "0x" || prefix == "0X") {
|
||||
return std::stoul(str.substr(2), nullptr, 16);
|
||||
}
|
||||
}
|
||||
return std::stoul(str);
|
||||
}
|
||||
|
||||
class Simulator {
|
||||
vluint64_t main_time = 0;
|
||||
vluint64_t max_sim_time = 10000;
|
||||
uint32_t halt_address = 0;
|
||||
size_t memory_words = 1024 * 1024; // 4MB
|
||||
bool dump_vcd = false;
|
||||
std::unique_ptr<VTop> top;
|
||||
std::unique_ptr<VCDTracer> vcd_tracer;
|
||||
std::unique_ptr<Memory> memory;
|
||||
bool dump_signature = false;
|
||||
unsigned long signature_begin, signature_end;
|
||||
std::string signature_filename;
|
||||
std::string instruction_filename;
|
||||
|
||||
public:
|
||||
void parse_args(std::vector<std::string> const& args) {
|
||||
if (auto it = std::find(args.begin(), args.end(), "-halt");
|
||||
it != args.end()) {
|
||||
halt_address = parse_number(*(it + 1));
|
||||
}
|
||||
|
||||
if (auto it = std::find(args.begin(), args.end(), "-memory");
|
||||
it != args.end()) {
|
||||
memory_words = std::stoul(*(it + 1));
|
||||
}
|
||||
|
||||
if (auto it = std::find(args.begin(), args.end(), "-time");
|
||||
it != args.end()) {
|
||||
max_sim_time = std::stoul(*(it + 1));
|
||||
}
|
||||
|
||||
if (auto it = std::find(args.begin(), args.end(), "-vcd");
|
||||
it != args.end()) {
|
||||
vcd_tracer->enable(*(it + 1), *top);
|
||||
}
|
||||
|
||||
if (auto it = std::find(args.begin(), args.end(), "-signature");
|
||||
it != args.end()) {
|
||||
dump_signature = true;
|
||||
signature_begin = parse_number(*(it + 1));
|
||||
signature_end = parse_number(*(it + 2));
|
||||
signature_filename = *(it + 3);
|
||||
}
|
||||
|
||||
if (auto it = std::find(args.begin(), args.end(), "-instruction");
|
||||
it != args.end()) {
|
||||
instruction_filename = *(it + 1);
|
||||
}
|
||||
}
|
||||
|
||||
Simulator(std::vector<std::string> const& args)
|
||||
: top(std::make_unique<VTop>()),
|
||||
vcd_tracer(std::make_unique<VCDTracer>()) {
|
||||
parse_args(args);
|
||||
memory = std::make_unique<Memory>(memory_words);
|
||||
if (!instruction_filename.empty()) {
|
||||
memory->load_binary(instruction_filename);
|
||||
}
|
||||
}
|
||||
|
||||
void run() {
|
||||
top->reset = 1;
|
||||
top->clock = 0;
|
||||
top->io_instruction_valid = 1;
|
||||
top->eval();
|
||||
vcd_tracer->dump(main_time);
|
||||
uint32_t data_memory_read_word = 0;
|
||||
uint32_t inst_memory_read_word = 0;
|
||||
uint32_t timer_interrupt = 0;
|
||||
uint32_t counter = 0;
|
||||
uint32_t clocktime = 1;
|
||||
bool memory_write_strobe[4] = {false};
|
||||
while (main_time < max_sim_time && !Verilated::gotFinish()) {
|
||||
++main_time;
|
||||
++counter;
|
||||
if(counter > clocktime){
|
||||
top->clock = !top->clock;
|
||||
counter = 0;
|
||||
}
|
||||
if(main_time & 0x00ff0 == 0xff0) {
|
||||
top->io_interrupt_flag = 1;
|
||||
} else{
|
||||
top->io_interrupt_flag = 0;
|
||||
}
|
||||
if (main_time > 2) {
|
||||
top->reset = 0;
|
||||
}
|
||||
// top->io_mem_slave_read_data = memory_read_word;
|
||||
top->io_memory_bundle_read_data = data_memory_read_word;
|
||||
top->io_instruction = inst_memory_read_word;
|
||||
top->clock = !top->clock;
|
||||
top->eval();
|
||||
top->io_interrupt_flag = 0;
|
||||
|
||||
data_memory_read_word = memory->read(top->io_memory_bundle_address);
|
||||
|
||||
|
||||
inst_memory_read_word = memory->readInst(top->io_instruction_address);
|
||||
|
||||
if (top->io_memory_bundle_write_enable) {
|
||||
memory_write_strobe[0] = top->io_memory_bundle_write_strobe_0;
|
||||
memory_write_strobe[1] = top->io_memory_bundle_write_strobe_1;
|
||||
memory_write_strobe[2] = top->io_memory_bundle_write_strobe_2;
|
||||
memory_write_strobe[3] = top->io_memory_bundle_write_strobe_3;
|
||||
memory->write(top->io_memory_bundle_address, top->io_memory_bundle_write_data,
|
||||
memory_write_strobe);
|
||||
}
|
||||
vcd_tracer->dump(main_time);
|
||||
if (halt_address) {
|
||||
if (memory->read(halt_address) == 0xBABECAFE) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (dump_signature) {
|
||||
char data[9] = {0};
|
||||
std::ofstream signature_file(signature_filename);
|
||||
for (size_t addr = signature_begin; addr < signature_end; addr += 4) {
|
||||
snprintf(data, 9, "%08x", memory->read(addr));
|
||||
signature_file << data << std::endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
~Simulator() {
|
||||
if (top) {
|
||||
top->final();
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
Verilated::commandArgs(argc, argv);
|
||||
std::vector<std::string> args(argv, argv + argc);
|
||||
Simulator simulator(args);
|
||||
simulator.run();
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user