init repo

lab3/src/test/scala/riscv/FiveStageCPUFinalTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+
+class FiveStageCPUFinalTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Five-stage Pipelined CPU with Reduced Branch Delay"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin", ImplementationType.FiveStageFinal)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin", ImplementationType.FiveStageFinal)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin", ImplementationType.FiveStageFinal)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+  it should "solve data and control hazards" in {
+    test(new TestTopModule("hazard.asmbin", ImplementationType.FiveStageFinal)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(26.U)
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(1.U)
+      c.io.mem_debug_read_address.poke(8.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(3.U)
+    }
+  }
+}

lab3/src/test/scala/riscv/FiveStageCPUForwardTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+
+class FiveStageCPUForwardTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Five-stage Pipelined CPU with Forwarding"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin", ImplementationType.FiveStageForward)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin", ImplementationType.FiveStageForward)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin", ImplementationType.FiveStageForward)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+  it should "solve data and control hazards" in {
+    test(new TestTopModule("hazard.asmbin", ImplementationType.FiveStageForward)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(27.U)
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(1.U)
+      c.io.mem_debug_read_address.poke(8.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(3.U)
+    }
+  }
+}

lab3/src/test/scala/riscv/FiveStageCPUStallTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+
+class FiveStageCPUStallTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Five-stage Pipelined CPU with Stalling"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin", ImplementationType.FiveStageStall)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin", ImplementationType.FiveStageStall)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin", ImplementationType.FiveStageStall)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+  it should "solve data and control hazards" in {
+    test(new TestTopModule("hazard.asmbin", ImplementationType.FiveStageStall)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(46.U)
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(1.U)
+      c.io.mem_debug_read_address.poke(8.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(3.U)
+    }
+  }
+}

lab3/src/test/scala/riscv/PipelineRegisterTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.core.PipelineRegister
+
+import scala.math.pow
+import scala.util.Random
+
+
+class PipelineRegisterTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Pipeline Register"
+  it should "be able to stall and flush" in {
+    val rand = new Random
+    val default_value = rand.nextInt(pow(2, Parameters.DataBits).toInt).asUInt(Parameters.DataWidth)
+    test(new PipelineRegister(Parameters.DataBits, default_value)).withAnnotations(TestAnnotations.annos) { c =>
+      var pre = default_value
+      for (_ <- 1 to 1000) {
+        val cur = rand.nextInt(pow(2, Parameters.DataBits).toInt).asUInt(Parameters.DataWidth)
+        c.io.in.poke(cur)
+        rand.nextInt(3) match {
+          case 0 =>
+            c.io.stall.poke(false.B)
+            c.io.flush.poke(false.B)
+            c.clock.step()
+            c.io.out.expect(cur)
+            pre = cur
+          case 1 =>
+            c.io.stall.poke(true.B)
+            c.io.flush.poke(false.B)
+            c.clock.step()
+            c.io.out.expect(pre)
+          case 2 =>
+            c.io.stall.poke(false.B)
+            c.io.flush.poke(true.B)
+            c.clock.step()
+            c.io.out.expect(default_value)
+            pre = default_value
+        }
+      }
+    }
+  }
+}

lab3/src/test/scala/riscv/TestAnnotations.scala

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+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
+import firrtl.AnnotationSeq
+
+import java.nio.file.{Files, Paths}
+
+object VerilatorEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("Path")) {
+    if (sys.env.getOrElse("Path", "").split(";").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  } else {
+    if (sys.env.getOrElse("PATH", "").split(":").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  }
+}
+
+object WriteVcdEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("WRITE_VCD")) {
+    Seq(WriteVcdAnnotation)
+  } else {
+    Seq()
+  }
+}
+
+object TestAnnotations {
+  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+}

lab3/src/test/scala/riscv/TestTopModule.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import peripheral.{InstructionROM, Memory, ROMLoader}
+import riscv.core.CPU
+
+class TestTopModule(exeFilename: String, implementation: Int) extends Module {
+  val io = IO(new Bundle {
+    val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val mem_debug_read_address = Input(UInt(Parameters.AddrWidth))
+    val regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val mem_debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+
+  val mem = Module(new Memory(8192))
+  val instruction_rom = Module(new InstructionROM(exeFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU(implementation))
+    cpu.io.debug_read_address := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+    cpu.io.interrupt_flag := 0.U
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      cpu.io.memory_bundle <> mem.io.bundle
+    }
+
+    cpu.io.debug_read_address := io.regs_debug_read_address
+    io.regs_debug_read_data := cpu.io.debug_read_data
+  }
+
+  mem.io.debug_read_address := io.mem_debug_read_address
+  io.mem_debug_read_data := mem.io.debug_read_data
+}

lab3/src/test/scala/riscv/ThreeStageCPUTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+
+class ThreeStageCPUTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Three-stage Pipelined CPU"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin", ImplementationType.ThreeStage)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin", ImplementationType.ThreeStage)).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin", ImplementationType.ThreeStage)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+  it should "solve control hazards" in {
+    test(new TestTopModule("hazard.asmbin", ImplementationType.ThreeStage)).withAnnotations(TestAnnotations.annos) { c =>
+      c.clock.step(1000)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(26.U)
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(1.U)
+      c.io.mem_debug_read_address.poke(8.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(3.U)
+    }
+  }
+}