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TOKISAKIX\21168
2023-12-11 21:50:22 +08:00
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54
lab3/src/main/scala/board/basys3/BCD2Segments.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.basys3
import chisel3._
import chisel3.util._
class BCD2Segments extends Module {
val io = IO(new Bundle {
val bcd = Input(UInt(4.W))
val segs = Output(UInt(8.W))
})
val bcd = io.bcd
val segs = Wire(UInt(8.W))
segs := MuxLookup(
bcd,
0xFF.U,
IndexedSeq(
0.U -> "b10000001".U,
1.U -> "b11001111".U,
2.U -> "b10010010".U,
3.U -> "b10000110".U,
4.U -> "b11001100".U,
5.U -> "b10100100".U,
6.U -> "b10100000".U,
7.U -> "b10001111".U,
8.U -> "b10000000".U,
9.U -> "b10000100".U,
10.U -> "b00001000".U,
11.U -> "b01100000".U,
12.U -> "b00110001".U,
13.U -> "b01000010".U,
14.U -> "b00110000".U,
15.U -> "b00111000".U,
)
)
io.segs := segs
}

32
lab3/src/main/scala/board/basys3/OnboardDigitDisplay.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.basys3
import chisel3._
class OnboardDigitDisplay extends Module {
val io = IO(new Bundle {
val digit_mask = Output(UInt(4.W))
})
val counter = RegInit(UInt(16.W), 0.U)
val digit_mask = RegInit(UInt(4.W), "b0111".U)
counter := counter + 1.U
when(counter === 0.U) {
digit_mask := (digit_mask << 1.U).asUInt + digit_mask(3)
}
io.digit_mask := digit_mask
}

34
lab3/src/main/scala/board/basys3/SYSULogo.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.basys3
import chisel3._
import chisel3.util._
class SYSULogo extends Module {
val io = IO(new Bundle {
val digit_mask = Input(UInt(4.W))
val segs = Output(UInt(8.W))
})
io.segs := MuxLookup(
io.digit_mask,
"b00100100".U, // "b0111".U, "b1101".U -> S
IndexedSeq(
"b1011".U -> "b01000100".U, // Y
"b1110".U -> "b01000001".U, // U
)
)
}

42
lab3/src/main/scala/board/basys3/SegmentMux.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.basys3
import chisel3._
import chisel3.util._
class SegmentMux extends Module {
val io = IO(new Bundle {
val digit_mask = Input(UInt(4.W))
val numbers = Input(UInt(16.W))
val segs = Output(UInt(8.W))
})
val digit = RegInit(UInt(4.W), 0.U)
val bcd2segs = Module(new BCD2Segments)
bcd2segs.io.bcd := digit
io.segs := bcd2segs.io.segs
digit := MuxLookup(
io.digit_mask,
io.numbers(3, 0), // "b1110".U
IndexedSeq(
"b1101".U -> io.numbers(7, 4),
"b1011".U -> io.numbers(11, 8),
"b0111".U -> io.numbers(15, 12)
)
)
}

128
lab3/src/main/scala/board/basys3/Top.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.basys3
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util._
import peripheral._
import riscv._
import riscv.core.CPU
class Top extends Module {
val binaryFilename = "tetris.asmbin"
val io = IO(new Bundle {
val switch = Input(UInt(16.W))
val segs = Output(UInt(8.W))
val digit_mask = Output(UInt(4.W))
val hsync = Output(Bool())
val vsync = Output(Bool())
val rgb = Output(UInt(12.W))
val led = Output(UInt(16.W))
val tx = Output(Bool())
val rx = Input(Bool())
})
val mem = Module(new Memory(Parameters.MemorySizeInWords))
val display = Module(new VGADisplay)
val timer = Module(new Timer)
val uart = Module(new Uart(frequency = 100000000, baudRate = 115200))
val dummy = Module(new Dummy)
display.io.bundle <> dummy.io.bundle
mem.io.bundle <> dummy.io.bundle
mem.io.debug_read_address := 0.U
timer.io.bundle <> dummy.io.bundle
uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd
uart.io.rxd := io.rx
val instruction_rom = Module(new InstructionROM(binaryFilename))
val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
rom_loader.io.rom_data := instruction_rom.io.data
rom_loader.io.load_address := Parameters.EntryAddress
instruction_rom.io.address := rom_loader.io.rom_address
val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
val CPU_tick = Wire(Bool())
val CPU_next = Wire(UInt(2.W))
CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
CPU_tick := CPU_clkdiv === 0.U
CPU_clkdiv := CPU_next
withClock(CPU_tick.asClock) {
val cpu = Module(new CPU(ImplementationType.FiveStageStall))
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
cpu.io.debug_read_address := 0.U
cpu.io.instruction_valid := rom_loader.io.load_finished
mem.io.instruction_address := cpu.io.instruction_address
cpu.io.instruction := mem.io.instruction
when(!rom_loader.io.load_finished) {
rom_loader.io.bundle <> mem.io.bundle
cpu.io.memory_bundle.read_data := 0.U
}.otherwise {
rom_loader.io.bundle.read_data := 0.U
when(cpu.io.device_select === 4.U) {
cpu.io.memory_bundle <> timer.io.bundle
}.elsewhen(cpu.io.device_select === 2.U) {
cpu.io.memory_bundle <> uart.io.bundle
}.elsewhen(cpu.io.device_select === 1.U) {
cpu.io.memory_bundle <> display.io.bundle
}.otherwise {
cpu.io.memory_bundle <> mem.io.bundle
}
}
}
io.hsync := display.io.hsync
io.vsync := display.io.vsync
io.rgb := display.io.rgb
mem.io.debug_read_address := io.switch(15, 1).asUInt << 2
io.led := Mux(
io.switch(0),
mem.io.debug_read_data(31, 16).asUInt,
mem.io.debug_read_data(15, 0).asUInt,
)
val onboard_display = Module(new OnboardDigitDisplay)
io.digit_mask := onboard_display.io.digit_mask
val sysu_logo = Module(new SYSULogo)
sysu_logo.io.digit_mask := io.digit_mask
val seg_mux = Module(new SegmentMux)
seg_mux.io.digit_mask := io.digit_mask
seg_mux.io.numbers := io.led
io.segs := MuxLookup(
io.switch,
seg_mux.io.segs,
IndexedSeq(
0.U -> sysu_logo.io.segs
)
)
}
object VerilogGenerator extends App {
(new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/basys3"), Seq(ChiselGeneratorAnnotation(() => new Top)))
}

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lab3/src/main/scala/board/pynq/Top.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.pynq
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util.Cat
import peripheral._
import riscv.core.CPU
import riscv.{ImplementationType, Parameters}
class Top extends Module {
val binaryFilename = "tetris.asmbin"
val io = IO(new Bundle() {
val hdmi_clk_n = Output(Bool())
val hdmi_clk_p = Output(Bool())
val hdmi_data_n = Output(UInt(3.W))
val hdmi_data_p = Output(UInt(3.W))
val hdmi_hpdn = Output(Bool())
val tx = Output(Bool())
val rx = Input(Bool())
val led = Output(UInt(4.W))
})
val mem = Module(new Memory(Parameters.MemorySizeInWords))
val display = Module(new HDMIDisplay)
val timer = Module(new Timer)
val uart = Module(new Uart(frequency = 125000000, baudRate = 115200))
val dummy = Module(new Dummy)
display.io.bundle <> dummy.io.bundle
mem.io.bundle <> dummy.io.bundle
mem.io.debug_read_address := 0.U
timer.io.bundle <> dummy.io.bundle
uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd
uart.io.rxd := io.rx
val instruction_rom = Module(new InstructionROM(binaryFilename))
val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
rom_loader.io.rom_data := instruction_rom.io.data
rom_loader.io.load_address := Parameters.EntryAddress
instruction_rom.io.address := rom_loader.io.rom_address
val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
val CPU_tick = Wire(Bool())
val CPU_next = Wire(UInt(2.W))
CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
CPU_tick := CPU_clkdiv === 0.U
CPU_clkdiv := CPU_next
withClock(CPU_tick.asClock) {
val cpu = Module(new CPU(implementation = ImplementationType.FiveStageStall))
val instruction_valid = RegNext(rom_loader.io.load_finished)
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
cpu.io.debug_read_address := 0.U
cpu.io.instruction_valid := instruction_valid
mem.io.instruction_address := cpu.io.instruction_address
cpu.io.instruction := mem.io.instruction
when(!rom_loader.io.load_finished) {
rom_loader.io.bundle <> mem.io.bundle
cpu.io.memory_bundle.read_data := 0.U
}.otherwise {
rom_loader.io.bundle.read_data := 0.U
when(cpu.io.device_select === 4.U) {
cpu.io.memory_bundle <> timer.io.bundle
}.elsewhen(cpu.io.device_select === 2.U) {
cpu.io.memory_bundle <> uart.io.bundle
}.elsewhen(cpu.io.device_select === 1.U) {
cpu.io.memory_bundle <> display.io.bundle
}.otherwise {
cpu.io.memory_bundle <> mem.io.bundle
}
}
}
io.led := 15.U(4.W)
io.hdmi_hpdn := 1.U
io.hdmi_data_n := display.io.TMDSdata_n
io.hdmi_data_p := display.io.TMDSdata_p
io.hdmi_clk_n := display.io.TMDSclk_n
io.hdmi_clk_p := display.io.TMDSclk_p
}
object VerilogGenerator extends App {
(new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/pynq"), Seq(ChiselGeneratorAnnotation(() => new Top)))
}

42
lab3/src/main/scala/board/verilator/Top.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package board.verilator
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import riscv.ImplementationType
import riscv.core.{CPU, CPUBundle}
class Top extends Module {
val io = IO(new CPUBundle)
val cpu = Module(new CPU(implementation = ImplementationType.ThreeStage))
io.device_select := 0.U
cpu.io.debug_read_address := io.debug_read_address
io.debug_read_data := cpu.io.debug_read_data
io.memory_bundle <> cpu.io.memory_bundle
io.instruction_address := cpu.io.instruction_address
cpu.io.instruction := io.instruction
cpu.io.interrupt_flag := io.interrupt_flag
cpu.io.instruction_valid := io.instruction_valid
}
object VerilogGenerator extends App {
(new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
new Top())))
}

29
lab3/src/main/scala/peripheral/Dummy.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import riscv.Parameters
// A dummy master that never initiates reads or writes
class Dummy extends Module {
val io = IO(new Bundle {
val bundle = Flipped(new RAMBundle)
})
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
io.bundle.write_data := 0.U
io.bundle.write_enable := false.B
io.bundle.address := 0.U
}

64
lab3/src/main/scala/peripheral/FontROM.scala Normal file
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package peripheral
import chisel3.experimental.{ChiselAnnotation, annotate}
import chisel3.util.experimental.loadMemoryFromFileInline
import chisel3.{Bundle, Input, Module, Output, SyncReadMem, UInt, _}
import firrtl.annotations.MemorySynthInit
import java.io.FileWriter
import java.nio.file.Paths
import javax.imageio.ImageIO
class FontROM(fontBitmapFilename: String = "vga_font_8x16.bmp") extends Module {
val glyphWidth = GlyphInfo.glyphWidth
val glyphHeight = GlyphInfo.glyphHeight
val io = IO(new Bundle {
val glyph_index = Input(UInt(7.W))
val glyph_y = Input(UInt(4.W))
val glyph_pixel_byte = Output(UInt(8.W))
})
annotate(new ChiselAnnotation {
override def toFirrtl =
MemorySynthInit
})
val (hexTxtPath, glyphCount) = readFontBitmap()
val mem = SyncReadMem(glyphCount, UInt(8.W))
loadMemoryFromFileInline(mem, hexTxtPath.toString.replaceAll("\\\\", "/"))
io.glyph_pixel_byte := mem.read(io.glyph_index * GlyphInfo.glyphHeight.U + io.glyph_y, true.B)
def readFontBitmap() = {
val inputStream = getClass.getClassLoader.getResourceAsStream(fontBitmapFilename)
val image = ImageIO.read(inputStream)
val glyphColumns = image.getWidth() / glyphWidth
val glyphRows = image.getHeight / glyphHeight
val glyphCount = glyphColumns * glyphRows
val glyphs = new Array[UInt](glyphCount * GlyphInfo.glyphHeight)
for (row <- 0 until glyphRows) {
for (col <- 0 until glyphColumns) {
for (i <- 0 until glyphHeight) {
var lineInt = 0
for (j <- 0 until glyphWidth) {
if (image.getRGB(col * glyphWidth + j, row * glyphHeight + i) != 0xFFFFFFFF) {
lineInt |= (1 << j)
}
}
glyphs((row * glyphColumns + col) * GlyphInfo.glyphHeight + i) = lineInt.U(8.W)
}
}
}
val currentDir = System.getProperty("user.dir")
val hexTxtPath = Paths.get(currentDir, "verilog", f"${fontBitmapFilename}.txt")
val writer = new FileWriter(hexTxtPath.toString)
for (i <- glyphs.indices) {
writer.write(f"@$i%x\n${glyphs(i).litValue}%02x\n")
}
writer.close()
(hexTxtPath, glyphs.length)
}
}

403
lab3/src/main/scala/peripheral/HDMIDisplay.scala Normal file
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// Copyright 2022 hrpccs
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import chisel3.util._
import riscv.Parameters
class HDMISync extends Module {
val io = IO(new Bundle {
val hsync = Output(Bool())
val vsync = Output(Bool())
val video_on = Output(Bool())
val p_tick = Output(Bool())
val f_tick = Output(Bool())
val x = Output(UInt(10.W))
val y = Output(UInt(10.W))
})
val DisplayHorizontal = ScreenInfo.DisplayHorizontal
val DisplayVertical = ScreenInfo.DisplayVertical
val BorderLeft = 48
val BorderRight = 16
val BorderTop = 10
val BorderBottom = 33
val RetraceHorizontal = 96
val RetraceVertical = 2
val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1
val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1
val RetraceHorizontalStart = DisplayHorizontal + BorderRight
val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1
val RetraceVerticalStart = DisplayVertical + BorderBottom
val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1
val pixel = RegInit(UInt(3.W), 0.U)
val pixel_next = Wire(UInt(3.W))
val pixel_tick = Wire(Bool())
val v_count_reg = RegInit(UInt(10.W), 0.U)
val h_count_reg = RegInit(UInt(10.W), 0.U)
val v_count_next = Wire(UInt(10.W))
val h_count_next = Wire(UInt(10.W))
val vsync_reg = RegInit(Bool(), false.B)
val hsync_reg = RegInit(Bool(), false.B)
val vsync_next = Wire(Bool())
val hsync_next = Wire(Bool())
pixel_next := Mux(pixel === 4.U, 0.U, pixel + 1.U)
pixel_tick := pixel === 0.U
h_count_next := Mux(
pixel_tick,
Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U),
h_count_reg
)
v_count_next := Mux(
pixel_tick && h_count_reg === MaxHorizontal.U,
Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U),
v_count_reg
)
hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U
vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U
pixel := pixel_next
hsync_reg := hsync_next
vsync_reg := vsync_next
v_count_reg := v_count_next
h_count_reg := h_count_next
io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U
io.hsync := hsync_reg
io.vsync := vsync_reg
io.x := h_count_reg
io.y := v_count_reg
io.p_tick := pixel_tick
io.f_tick := io.x === 0.U && io.y === 0.U
}
class TMDS_encoder extends Module {
val io = IO(new Bundle() {
val video_data = Input(UInt(8.W)) //r,g,b,8bit
val control_data = Input(UInt(2.W))
val video_on = Input(Bool())
val TMDS = Output(UInt(10.W))
})
val Nb1s = PopCount(io.video_data)
val XNOR = Wire(Bool())
XNOR := (Nb1s > 4.U(4.W)) || (Nb1s === 4.U(4.W) && io.video_data(0) === 0.U)
val xored = 1.U(1.W) ## xorfunc(io.video_data)
val xnored = 0.U(1.W) ## xnorfunc(io.video_data)
val q_m = Mux(
XNOR,
xnored,
xored
)
val diff = PopCount(q_m).asSInt - 4.S
val diffSize = diff.getWidth
val disparitySize = 4
val disparityReg = RegInit(0.S(disparitySize.W))
val doutReg = RegInit("b1010101011".U(10.W))
//using recursion to compute
def xorfunc(value: UInt): UInt = {
value.getWidth match {
case 1 => value(0)
case s => val res = xorfunc(VecInit(value.asBools.drop(1)).asUInt)
value.asBools.head ^ res.asBools.head ## res
}
}
def xnorfunc(value: UInt): UInt = {
value.getWidth match {
case 1 => value(0)
case s => val res = xnorfunc(VecInit(value.asBools.drop(1)).asUInt)
!(value.asBools.head ^ res.asBools.head) ## res
}
}
when(io.video_on === false.B) {
disparityReg := 0.S
doutReg := "b1010101011".U(10.W)
switch(io.control_data) {
is("b00".U(2.W)) {
doutReg := "b1101010100".U(10.W)
}
is("b01".U(2.W)) {
doutReg := "b0010101011".U(10.W)
}
is("b10".U(2.W)) {
doutReg := "b0101010100".U(10.W)
}
}
}.otherwise {
when(disparityReg === 0.S || diff === 0.S) {
when(q_m(8) === false.B) {
doutReg := "b10".U(2.W) ## q_m(7, 0)
disparityReg := disparityReg - diff
}.otherwise {
doutReg := "b01".U(2.W) ## q_m(7, 0)
disparityReg := disparityReg + diff
}
}.elsewhen((!diff(diffSize - 1) && !disparityReg(disparitySize - 1))
|| (diff(diffSize - 1) && disparityReg(disparitySize - 1))) {
doutReg := 1.U(1.W) ## q_m(8) ## ~q_m(7, 0)
when(q_m(8)) {
disparityReg := disparityReg + 1.S - diff
}.otherwise {
disparityReg := disparityReg - diff
}
}.otherwise {
doutReg := 0.U(1.W) ## q_m
when(q_m(8)) {
disparityReg := disparityReg + diff
}.otherwise {
disparityReg := disparityReg - 1.S + diff
}
}
}
io.TMDS := doutReg
}
class HDMIDisplay extends Module {
val io = IO(new Bundle() {
val bundle = new RAMBundle
val TMDSclk_p = Output(Bool())
val TMDSdata_p = Output(UInt(3.W))
val TMDSclk_n = Output(Bool())
val TMDSdata_n = Output(UInt(3.W))
})
val mem = Module(new BlockRAM(ScreenInfo.Chars / Parameters.WordSize))
mem.io.write_enable := io.bundle.write_enable
mem.io.write_data := io.bundle.write_data
mem.io.write_address := io.bundle.address
mem.io.write_strobe := io.bundle.write_strobe
mem.io.read_address := io.bundle.address
io.bundle.read_data := mem.io.read_data
val pixel_clk = Wire(Bool())
val hsync = Wire(Bool())
val vsync = Wire(Bool())
val sync = Module(new HDMISync)
hsync := sync.io.hsync
vsync := sync.io.vsync
pixel_clk := sync.io.p_tick
val font_rom = Module(new FontROM)
val row = (sync.io.y >> log2Up(GlyphInfo.glyphHeight)).asUInt
val col = (sync.io.x >> log2Up(GlyphInfo.glyphWidth)).asUInt
val char_index = (row * ScreenInfo.CharCols.U) + col
val offset = char_index(1, 0)
val ch = Wire(UInt(8.W))
mem.io.debug_read_address := char_index
ch := MuxLookup(
offset,
0.U,
IndexedSeq(
0.U -> mem.io.debug_read_data(7, 0).asUInt,
1.U -> mem.io.debug_read_data(15, 8).asUInt,
2.U -> mem.io.debug_read_data(23, 16).asUInt,
3.U -> mem.io.debug_read_data(31, 24).asUInt
)
)
font_rom.io.glyph_index := Mux(ch >= 32.U, ch - 31.U, 0.U)
font_rom.io.glyph_y := sync.io.y(log2Up(GlyphInfo.glyphHeight) - 1, 0)
val rgb = Wire(UInt(24.W)) //RGB 8:8:8
// White if pixel_on and glyph pixel on
val glyph_x = sync.io.x(log2Up(GlyphInfo.glyphWidth) - 1, 0)
rgb := Mux(sync.io.video_on && font_rom.io.glyph_pixel_byte(glyph_x), 0xFFFFFFF.U, 0.U)
//TMDS_PLLVR is a vivado IP core, check it in /verilog/pynq/TMDS_PLLVR.v
val serial_clk = Wire(Clock())
val pll_lock = Wire(Bool())
val tmdspll = Module(new TMDS_PLLVR)
val rst = Wire(Reset())
tmdspll.io.clkin := pixel_clk.asClock
serial_clk := tmdspll.io.clkout
pll_lock := tmdspll.io.lock
tmdspll.io.reset := reset
rst := ~pll_lock
val tmds = Wire(UInt(3.W))
val tmds_clk = Wire(Bool())
withClockAndReset(pixel_clk.asClock, rst) {
val tmds_channel1 = Wire(UInt(10.W))
val tmds_channel2 = Wire(UInt(10.W))
val tmds_channel0 = Wire(UInt(10.W))
val tmds_green = Module(new TMDS_encoder)
val tmds_red = Module(new TMDS_encoder)
val tmds_blue = Module(new TMDS_encoder)
tmds_red.io.video_on := sync.io.video_on
tmds_blue.io.video_on := sync.io.video_on
tmds_green.io.video_on := sync.io.video_on
tmds_blue.io.control_data := sync.io.vsync ## sync.io.hsync
tmds_green.io.control_data := 0.U
tmds_red.io.control_data := 0.U
tmds_red.io.video_data := rgb(23, 16)
tmds_blue.io.video_data := rgb(15, 8)
tmds_green.io.video_data := rgb(7, 0)
tmds_channel0 := tmds_blue.io.TMDS
tmds_channel1 := tmds_green.io.TMDS
tmds_channel2 := tmds_red.io.TMDS
val serdesBlue = Module(new Oser10Module())
serdesBlue.io.data := tmds_channel0
serdesBlue.io.fclk := serial_clk
val serdesGreen = Module(new Oser10Module())
serdesGreen.io.data := tmds_channel1
serdesGreen.io.fclk := serial_clk
val serdesRed = Module(new Oser10Module())
serdesRed.io.data := tmds_channel2
serdesRed.io.fclk := serial_clk
tmds := serdesRed.io.q ## serdesGreen.io.q ## serdesBlue.io.q
//serdesCLk : 25Mhz ,Why not directly use p_tick?
//cause Duty Ratio of p_tick is 10% , while which of serdesCLk is 50%
val serdesClk = Module(new Oser10Module())
serdesClk.io.data := "b1111100000".U(10.W)
serdesClk.io.fclk := serial_clk
tmds_clk := serdesClk.io.q
val buffDiffBlue = Module(new OBUFDS)
buffDiffBlue.io.I := tmds(0)
val buffDiffGreen = Module(new OBUFDS)
buffDiffGreen.io.I := tmds(1)
val buffDiffRed = Module(new OBUFDS)
buffDiffRed.io.I := tmds(2)
val buffDiffClk = Module(new OBUFDS)
buffDiffClk.io.I := tmds_clk
io.TMDSclk_p := buffDiffClk.io.O
io.TMDSclk_n := buffDiffClk.io.OB
io.TMDSdata_p := buffDiffRed.io.O ## buffDiffGreen.io.O ## buffDiffBlue.io.O
io.TMDSdata_n := buffDiffRed.io.OB ## buffDiffGreen.io.OB ## buffDiffBlue.io.OB
}
}
//----------------------------------------
//PLL frequency multiplier using BlackBox
class TMDS_PLLVR extends BlackBox {
val io = IO(new Bundle {
val clkin = Input(Clock())
val reset = Input(Reset())
val clkout = Output(Clock())
val clkoutd = Output(Clock())
val lock = Output(Bool())
})
}
/* OSER10 : serializer 10:1*/
class OSER10 extends Module {
val io = IO(new Bundle {
val Q = Output(Bool()) // OSER10 data output signal
val D0 = Input(Bool())
val D1 = Input(Bool())
val D2 = Input(Bool())
val D3 = Input(Bool())
val D4 = Input(Bool())
val D5 = Input(Bool())
val D6 = Input(Bool())
val D7 = Input(Bool())
val D8 = Input(Bool())
val D9 = Input(Bool()) // OSER10 data input signal
val PCLK = Input(Clock()) // Primary clock input signal
val FCLK = Input(Clock()) // High speed clock input signal
val RESET = Input(Reset()) // Asynchronous reset input signal,
//active-high.
})
withClockAndReset(io.FCLK, io.RESET) {
val count = RegInit(0.U(4.W))
val countnext = Wire(UInt(4.W))
io.Q := MuxLookup(
count,
0.U,
IndexedSeq(
0.U -> io.D0.asBool,
1.U -> io.D1.asBool,
2.U -> io.D2.asBool,
3.U -> io.D3.asBool,
4.U -> io.D4.asBool,
5.U -> io.D5.asBool,
6.U -> io.D6.asBool,
7.U -> io.D7.asBool,
8.U -> io.D8.asBool,
9.U -> io.D9.asBool
)
)
countnext := Mux(
count === 9.U, 0.U, count + 1.U
)
count := countnext
}
}
class Oser10Module extends Module {
val io = IO(new Bundle {
val q = Output(Bool())
val data = Input(UInt(10.W))
val fclk = Input(Clock()) // Fast clock
})
val osr10 = Module(new OSER10())
io.q := osr10.io.Q
osr10.io.D0 := io.data(0)
osr10.io.D1 := io.data(1)
osr10.io.D2 := io.data(2)
osr10.io.D3 := io.data(3)
osr10.io.D4 := io.data(4)
osr10.io.D5 := io.data(5)
osr10.io.D6 := io.data(6)
osr10.io.D7 := io.data(7)
osr10.io.D8 := io.data(8)
osr10.io.D9 := io.data(9)
osr10.io.PCLK := clock
osr10.io.FCLK := io.fclk
osr10.io.RESET := reset
}
/* lvds output */
class OBUFDS extends BlackBox {
val io = IO(new Bundle {
val O = Output(Bool())
val OB = Output(Bool())
val I = Input(Bool())
})
}
//-----------------------------------------

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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import chisel3.experimental.{ChiselAnnotation, annotate}
import chisel3.util.experimental.loadMemoryFromFileInline
import firrtl.annotations.MemorySynthInit
import riscv.Parameters
import java.io.FileWriter
import java.nio.file.{Files, Paths}
import java.nio.{ByteBuffer, ByteOrder}
class InstructionROM(instructionFilename: String) extends Module {
val io = IO(new Bundle {
val address = Input(UInt(Parameters.AddrWidth))
val data = Output(UInt(Parameters.InstructionWidth))
})
val (instructionsInitFile, capacity) = readAsmBinary(instructionFilename)
val mem = Mem(capacity, UInt(Parameters.InstructionWidth))
annotate(new ChiselAnnotation {
override def toFirrtl =
MemorySynthInit
})
loadMemoryFromFileInline(mem, instructionsInitFile.toString.replaceAll("\\\\", "/"))
io.data := mem.read(io.address)
def readAsmBinary(filename: String) = {
val inputStream = if (Files.exists(Paths.get(filename))) {
Files.newInputStream(Paths.get(filename))
} else {
getClass.getClassLoader.getResourceAsStream(filename)
}
var instructions = new Array[BigInt](0)
val arr = new Array[Byte](4)
while (inputStream.read(arr) == 4) {
val instBuf = ByteBuffer.wrap(arr)
instBuf.order(ByteOrder.LITTLE_ENDIAN)
val inst = BigInt(instBuf.getInt() & 0xFFFFFFFFL)
instructions = instructions :+ inst
}
instructions = instructions :+ BigInt(0x00000013L)
instructions = instructions :+ BigInt(0x00000013L)
instructions = instructions :+ BigInt(0x00000013L)
val currentDir = System.getProperty("user.dir")
val exeTxtPath = Paths.get(currentDir, "verilog", f"${instructionFilename}.txt")
val writer = new FileWriter(exeTxtPath.toString)
for (i <- instructions.indices) {
writer.write(f"@$i%x\n${instructions(i)}%08x\n")
}
writer.close()
(exeTxtPath, instructions.length)
}
}

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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import riscv.Parameters
class RAMBundle extends Bundle {
val address = Input(UInt(Parameters.AddrWidth))
val write_data = Input(UInt(Parameters.DataWidth))
val write_enable = Input(Bool())
val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
val read_data = Output(UInt(Parameters.DataWidth))
}
// The purpose of this module is to help the synthesis tool recognize
// our memory as a Block RAM template
class BlockRAM(capacity: Int) extends Module {
val io = IO(new Bundle {
val read_address = Input(UInt(Parameters.AddrWidth))
val write_address = Input(UInt(Parameters.AddrWidth))
val write_data = Input(UInt(Parameters.DataWidth))
val write_enable = Input(Bool())
val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
val debug_read_address = Input(UInt(Parameters.AddrWidth))
val read_data = Output(UInt(Parameters.DataWidth))
val debug_read_data = Output(UInt(Parameters.DataWidth))
})
val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
when(io.write_enable) {
val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
for (i <- 0 until Parameters.WordSize) {
write_data_vec(i) := io.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
}
mem.write((io.write_address >> 2.U).asUInt, write_data_vec, io.write_strobe)
}
io.read_data := mem.read((io.read_address >> 2.U).asUInt, true.B).asUInt
io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
}
class Memory(capacity: Int) extends Module {
val io = IO(new Bundle {
val bundle = new RAMBundle
val instruction = Output(UInt(Parameters.DataWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val debug_read_address = Input(UInt(Parameters.AddrWidth))
val debug_read_data = Output(UInt(Parameters.DataWidth))
})
val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
when(io.bundle.write_enable) {
val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
for (i <- 0 until Parameters.WordSize) {
write_data_vec(i) := io.bundle.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
}
mem.write((io.bundle.address >> 2.U).asUInt, write_data_vec, io.bundle.write_strobe)
}
io.bundle.read_data := mem.read((io.bundle.address >> 2.U).asUInt, true.B).asUInt
io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
io.instruction := mem.read((io.instruction_address >> 2.U).asUInt, true.B).asUInt
}

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lab3/src/main/scala/peripheral/ROMLoader.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import riscv.Parameters
class ROMLoader(capacity: Int) extends Module {
val io = IO(new Bundle {
val bundle = Flipped(new RAMBundle)
val rom_address = Output(UInt(Parameters.AddrWidth))
val rom_data = Input(UInt(Parameters.InstructionWidth))
val load_address = Input(UInt(Parameters.AddrWidth))
val load_finished = Output(Bool())
})
val address = RegInit(0.U(32.W))
val valid = RegInit(false.B)
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
io.bundle.address := 0.U
io.bundle.write_data := 0.U
io.bundle.write_enable := false.B
when(address <= (capacity - 1).U) {
io.bundle.write_enable := true.B
io.bundle.write_data := io.rom_data
io.bundle.address := (address << 2.U).asUInt + io.load_address
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B))
address := address + 1.U
when(address === (capacity - 1).U) {
valid := true.B
}
}
io.load_finished := valid
io.rom_address := address
}

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lab3/src/main/scala/peripheral/Timer.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import chisel3.util._
import riscv.Parameters
class Timer extends Module {
val io = IO(new Bundle {
val bundle = new RAMBundle
val signal_interrupt = Output(Bool())
val debug_limit = Output(UInt(Parameters.DataWidth))
val debug_enabled = Output(Bool())
})
val count = RegInit(0.U(32.W))
val limit = RegInit(100000000.U(32.W))
io.debug_limit := limit
val enabled = RegInit(true.B)
io.debug_enabled := enabled
io.bundle.read_data := MuxLookup(
io.bundle.address,
0.U,
IndexedSeq(
0x4.U -> limit,
0x8.U -> enabled.asUInt,
)
)
when(io.bundle.write_enable) {
when(io.bundle.address === 0x4.U) {
limit := io.bundle.write_data
count := 0.U
}.elsewhen(io.bundle.address === 0x8.U) {
enabled := io.bundle.write_data =/= 0.U
}
}
io.signal_interrupt := enabled && (count >= (limit - 10.U))
when(count >= limit) {
count := 0.U
}.otherwise {
count := count + 1.U
}
}

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lab3/src/main/scala/peripheral/UART.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import chisel3.util._
class UartIO extends DecoupledIO(UInt(8.W)) {
}
/**
* Transmit part of the UART.
* A minimal version without any additional buffering.
* Use a ready/valid handshaking.
*/
class Tx(frequency: Int, baudRate: Int) extends Module {
val io = IO(new Bundle {
val txd = Output(UInt(1.W))
val channel = Flipped(new UartIO())
})
val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
val shiftReg = RegInit(0x7ff.U)
val cntReg = RegInit(0.U(20.W))
val bitsReg = RegInit(0.U(4.W))
io.channel.ready := (cntReg === 0.U) && (bitsReg === 0.U)
io.txd := shiftReg(0)
when(cntReg === 0.U) {
cntReg := BIT_CNT
when(bitsReg =/= 0.U) {
val shift = shiftReg >> 1
shiftReg := Cat(1.U, shift(9, 0))
bitsReg := bitsReg - 1.U
}.otherwise {
when(io.channel.valid) {
shiftReg := Cat(Cat(3.U, io.channel.bits), 0.U) // two stop bits, data, one start bit
bitsReg := 11.U
}.otherwise {
shiftReg := 0x7ff.U
}
}
}.otherwise {
cntReg := cntReg - 1.U
}
}
/**
* Receive part of the UART.
* A minimal version without any additional buffering.
* Use a ready/valid handshaking.
*
* The following code is inspired by Tommy's receive code at:
* https://github.com/tommythorn/yarvi
*/
class Rx(frequency: Int, baudRate: Int) extends Module {
val io = IO(new Bundle {
val rxd = Input(UInt(1.W))
val channel = new UartIO()
})
val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U
// Sync in the asynchronous RX data, reset to 1 to not start reading after a reset
val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U)
val shiftReg = RegInit(0.U(8.W))
val cntReg = RegInit(0.U(20.W))
val bitsReg = RegInit(0.U(4.W))
val valReg = RegInit(false.B)
when(cntReg =/= 0.U) {
cntReg := cntReg - 1.U
}.elsewhen(bitsReg =/= 0.U) {
cntReg := BIT_CNT
shiftReg := Cat(rxReg, shiftReg >> 1)
bitsReg := bitsReg - 1.U
// the last shifted in
when(bitsReg === 1.U) {
valReg := true.B
}
}.elsewhen(rxReg === 0.U) { // wait 1.5 bits after falling edge of start
cntReg := START_CNT
bitsReg := 8.U
}
when(valReg && io.channel.ready) {
valReg := false.B
}
io.channel.bits := shiftReg
io.channel.valid := valReg
}
/**
* A single byte buffer with a ready/valid interface
*/
class Buffer extends Module {
val io = IO(new Bundle {
val in = Flipped(new UartIO())
val out = new UartIO()
})
val empty :: full :: Nil = Enum(2)
val stateReg = RegInit(empty)
val dataReg = RegInit(0.U(8.W))
io.in.ready := stateReg === empty
io.out.valid := stateReg === full
when(stateReg === empty) {
when(io.in.valid) {
dataReg := io.in.bits
stateReg := full
}
}.otherwise { // full
when(io.out.ready) {
stateReg := empty
}
}
io.out.bits := dataReg
}
/**
* A transmitter with a single buffer.
*/
class BufferedTx(frequency: Int, baudRate: Int) extends Module {
val io = IO(new Bundle {
val txd = Output(UInt(1.W))
val channel = Flipped(new UartIO())
})
val tx = Module(new Tx(frequency, baudRate))
val buf = Module(new Buffer)
buf.io.in <> io.channel
tx.io.channel <> buf.io.out
io.txd <> tx.io.txd
}
class Uart(frequency: Int, baudRate: Int) extends Module {
val io = IO(new Bundle {
val bundle = new RAMBundle
val rxd = Input(UInt(1.W))
val txd = Output(UInt(1.W))
val signal_interrupt = Output(Bool())
})
val interrupt = RegInit(false.B)
val rxData = RegInit(0.U)
val tx = Module(new BufferedTx(frequency, baudRate))
val rx = Module(new Rx(frequency, baudRate))
io.bundle.read_data := 0.U
when(io.bundle.address === 0x4.U) {
io.bundle.read_data := baudRate.U
}.elsewhen(io.bundle.address === 0xC.U) {
io.bundle.read_data := rxData
interrupt := false.B
}
tx.io.channel.valid := false.B
tx.io.channel.bits := 0.U
when(io.bundle.write_enable) {
when(io.bundle.address === 0x8.U) {
interrupt := io.bundle.write_data =/= 0.U
}.elsewhen(io.bundle.address === 0x10.U) {
tx.io.channel.valid := true.B
tx.io.channel.bits := io.bundle.write_data
}
}
io.txd := tx.io.txd
rx.io.rxd := io.rxd
io.signal_interrupt := interrupt
rx.io.channel.ready := false.B
when(rx.io.channel.valid) {
rx.io.channel.ready := true.B
rxData := rx.io.channel.bits
interrupt := true.B
}
}

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lab3/src/main/scala/peripheral/VGADisplay.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package peripheral
import chisel3._
import chisel3.util._
import riscv.Parameters
object GlyphInfo {
val glyphWidth = 8
val glyphHeight = 16
// ASCII printable characters start from here
val spaceIndex = 1
}
object ScreenInfo {
val DisplayHorizontal = 640
val DisplayVertical = 480
val CharCols = DisplayHorizontal / GlyphInfo.glyphWidth
val CharRows = DisplayVertical / GlyphInfo.glyphHeight
val Chars = CharCols * CharRows
}
class VGASync extends Module {
val io = IO(new Bundle {
val hsync = Output(Bool())
val vsync = Output(Bool())
val video_on = Output(Bool())
val p_tick = Output(Bool())
val f_tick = Output(Bool())
val x = Output(UInt(10.W))
val y = Output(UInt(10.W))
})
val DisplayHorizontal = ScreenInfo.DisplayHorizontal
val DisplayVertical = ScreenInfo.DisplayVertical
val BorderLeft = 48
val BorderRight = 16
val BorderTop = 10
val BorderBottom = 33
val RetraceHorizontal = 96
val RetraceVertical = 2
val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1
val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1
val RetraceHorizontalStart = DisplayHorizontal + BorderRight
val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1
val RetraceVerticalStart = DisplayVertical + BorderBottom
val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1
val pixel = RegInit(UInt(2.W), 0.U)
val pixel_next = Wire(UInt(2.W))
val pixel_tick = Wire(Bool())
val v_count_reg = RegInit(UInt(10.W), 0.U)
val h_count_reg = RegInit(UInt(10.W), 0.U)
val v_count_next = Wire(UInt(10.W))
val h_count_next = Wire(UInt(10.W))
val vsync_reg = RegInit(Bool(), false.B)
val hsync_reg = RegInit(Bool(), false.B)
val vsync_next = Wire(Bool())
val hsync_next = Wire(Bool())
pixel_next := pixel + 1.U
pixel_tick := pixel === 0.U
h_count_next := Mux(
pixel_tick,
Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U),
h_count_reg
)
v_count_next := Mux(
pixel_tick && h_count_reg === MaxHorizontal.U,
Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U),
v_count_reg
)
hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U
vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U
pixel := pixel_next
hsync_reg := hsync_next
vsync_reg := vsync_next
v_count_reg := v_count_next
h_count_reg := h_count_next
io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U
io.hsync := hsync_reg
io.vsync := vsync_reg
io.x := h_count_reg
io.y := v_count_reg
io.p_tick := pixel_tick
io.f_tick := io.x === 0.U && io.y === 0.U
}
class VGADisplay extends Module {
val io = IO(new Bundle() {
val bundle = new RAMBundle
val hsync = Output(Bool())
val vsync = Output(Bool())
val rgb = Output(UInt(12.W))
})
val mem = Module(new BlockRAM(ScreenInfo.Chars / Parameters.WordSize))
mem.io.write_enable := io.bundle.write_enable
mem.io.write_data := io.bundle.write_data
mem.io.write_address := io.bundle.write_data
mem.io.write_strobe := io.bundle.write_strobe
mem.io.read_address := io.bundle.address
io.bundle.read_data := mem.io.read_data
val sync = Module(new VGASync)
io.hsync := sync.io.hsync
io.vsync := sync.io.vsync
val font_rom = Module(new FontROM)
val row = (sync.io.y >> log2Up(GlyphInfo.glyphHeight)).asUInt
val col = (sync.io.x >> log2Up(GlyphInfo.glyphWidth)).asUInt
val char_index = (row * ScreenInfo.CharCols.U) + col
val offset = char_index(1, 0)
val ch = Wire(UInt(8.W))
mem.io.debug_read_address := char_index
ch := MuxLookup(
offset,
0.U,
IndexedSeq(
0.U -> mem.io.debug_read_data(7, 0).asUInt,
1.U -> mem.io.debug_read_data(15, 8).asUInt,
2.U -> mem.io.debug_read_data(23, 16).asUInt,
3.U -> mem.io.debug_read_data(31, 24).asUInt
)
)
font_rom.io.glyph_index := Mux(ch >= 32.U, ch - 31.U, 0.U)
font_rom.io.glyph_y := sync.io.y(log2Up(GlyphInfo.glyphHeight) - 1, 0)
// White if pixel_on and glyph pixel on
val glyph_x = sync.io.x(log2Up(GlyphInfo.glyphWidth) - 1, 0)
io.rgb := Mux(sync.io.video_on && font_rom.io.glyph_pixel_byte(glyph_x), 0xFFFF.U, 0.U)
}

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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv
import chisel3._
import chisel3.util._
object ImplementationType {
val ThreeStage = 0
val FiveStageStall = 1
val FiveStageForward = 2
val FiveStageFinal = 3
}
object Parameters {
val AddrBits = 32
val AddrWidth = AddrBits.W
val InstructionBits = 32
val InstructionWidth = InstructionBits.W
val DataBits = 32
val DataWidth = DataBits.W
val ByteBits = 8
val ByteWidth = ByteBits.W
val WordSize = Math.ceil(DataBits / ByteBits).toInt
val PhysicalRegisters = 32
val PhysicalRegisterAddrBits = log2Up(PhysicalRegisters)
val PhysicalRegisterAddrWidth = PhysicalRegisterAddrBits.W
val CSRRegisterAddrBits = 12
val CSRRegisterAddrWidth = CSRRegisterAddrBits.W
val InterruptFlagBits = 32
val InterruptFlagWidth = InterruptFlagBits.W
val HoldStateBits = 3
val StallStateWidth = HoldStateBits.W
val MemorySizeInBytes = 32768
val MemorySizeInWords = MemorySizeInBytes / 4
val EntryAddress = 0x1000.U(Parameters.AddrWidth)
val MasterDeviceCount = 1
val SlaveDeviceCount = 8
val SlaveDeviceCountBits = log2Up(Parameters.SlaveDeviceCount)
}

69
lab3/src/main/scala/riscv/core/ALU.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import chisel3.experimental.ChiselEnum
import chisel3.util._
import riscv.Parameters
object ALUFunctions extends ChiselEnum {
val zero, add, sub, sll, slt, xor, or, and, srl, sra, sltu = Value
}
class ALU extends Module {
val io = IO(new Bundle {
val func = Input(ALUFunctions())
val op1 = Input(UInt(Parameters.DataWidth))
val op2 = Input(UInt(Parameters.DataWidth))
val result = Output(UInt(Parameters.DataWidth))
})
io.result := 0.U
switch(io.func) {
is(ALUFunctions.add) {
io.result := io.op1 + io.op2
}
is(ALUFunctions.sub) {
io.result := io.op1 - io.op2
}
is(ALUFunctions.sll) {
io.result := io.op1 << io.op2(4, 0)
}
is(ALUFunctions.slt) {
io.result := io.op1.asSInt < io.op2.asSInt
}
is(ALUFunctions.xor) {
io.result := io.op1 ^ io.op2
}
is(ALUFunctions.or) {
io.result := io.op1 | io.op2
}
is(ALUFunctions.and) {
io.result := io.op1 & io.op2
}
is(ALUFunctions.srl) {
io.result := io.op1 >> io.op2(4, 0)
}
is(ALUFunctions.sra) {
io.result := (io.op1.asSInt >> io.op2(4, 0)).asUInt
}
is(ALUFunctions.sltu) {
io.result := io.op1 < io.op2
}
}
}

87
lab3/src/main/scala/riscv/core/ALUControl.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import chisel3.util._
import riscv.core.threestage.{InstructionTypes, Instructions, InstructionsTypeI, InstructionsTypeR}
class ALUControl extends Module {
val io = IO(new Bundle {
val opcode = Input(UInt(7.W))
val funct3 = Input(UInt(3.W))
val funct7 = Input(UInt(7.W))
val alu_funct = Output(ALUFunctions())
})
io.alu_funct := ALUFunctions.zero
switch(io.opcode) {
is(InstructionTypes.I) {
io.alu_funct := MuxLookup(
io.funct3,
ALUFunctions.zero,
IndexedSeq(
InstructionsTypeI.addi -> ALUFunctions.add,
InstructionsTypeI.slli -> ALUFunctions.sll,
InstructionsTypeI.slti -> ALUFunctions.slt,
InstructionsTypeI.sltiu -> ALUFunctions.sltu,
InstructionsTypeI.xori -> ALUFunctions.xor,
InstructionsTypeI.ori -> ALUFunctions.or,
InstructionsTypeI.andi -> ALUFunctions.and,
InstructionsTypeI.sri -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
),
)
}
is(InstructionTypes.RM) {
io.alu_funct := MuxLookup(
io.funct3,
ALUFunctions.zero,
IndexedSeq(
InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add),
InstructionsTypeR.sll -> ALUFunctions.sll,
InstructionsTypeR.slt -> ALUFunctions.slt,
InstructionsTypeR.sltu -> ALUFunctions.sltu,
InstructionsTypeR.xor -> ALUFunctions.xor,
InstructionsTypeR.or -> ALUFunctions.or,
InstructionsTypeR.and -> ALUFunctions.and,
InstructionsTypeR.sr -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
),
)
}
is(InstructionTypes.B) {
io.alu_funct := ALUFunctions.add
}
is(InstructionTypes.L) {
io.alu_funct := ALUFunctions.add
}
is(InstructionTypes.S) {
io.alu_funct := ALUFunctions.add
}
is(Instructions.jal) {
io.alu_funct := ALUFunctions.add
}
is(Instructions.jalr) {
io.alu_funct := ALUFunctions.add
}
is(Instructions.lui) {
io.alu_funct := ALUFunctions.add
}
is(Instructions.auipc) {
io.alu_funct := ALUFunctions.add
}
}
}

40
lab3/src/main/scala/riscv/core/CPU.scala Normal file
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// Copyright 2022 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import riscv.ImplementationType
import riscv.core.fivestage_final.{CPU => FiveStageCPUFinal}
import riscv.core.fivestage_forward.{CPU => FiveStageCPUForward}
import riscv.core.fivestage_stall.{CPU => FiveStageCPUStall}
import riscv.core.threestage.{CPU => ThreeStageCPU}
class CPU(val implementation: Int = ImplementationType.FiveStageFinal) extends Module {
val io = IO(new CPUBundle)
implementation match {
case ImplementationType.ThreeStage =>
val cpu = Module(new ThreeStageCPU)
cpu.io <> io
case ImplementationType.FiveStageStall =>
val cpu = Module(new FiveStageCPUStall)
cpu.io <> io
case ImplementationType.FiveStageForward =>
val cpu = Module(new FiveStageCPUForward)
cpu.io <> io
case _ =>
val cpu = Module(new FiveStageCPUFinal)
cpu.io <> io
}
}

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lab3/src/main/scala/riscv/core/CPUBundle.scala Normal file
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// Copyright 2022 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import peripheral.RAMBundle
import riscv.Parameters
class CPUBundle extends Bundle {
val instruction_address = Output(UInt(Parameters.AddrWidth))
val instruction = Input(UInt(Parameters.DataWidth))
val instruction_valid = Input(Bool())
val memory_bundle = Flipped(new RAMBundle)
val device_select = Output(UInt(Parameters.SlaveDeviceCountBits.W))
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val debug_read_data = Output(UInt(Parameters.DataWidth))
}

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lab3/src/main/scala/riscv/core/CSR.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import chisel3.util._
import riscv.Parameters
import riscv.core.threestage.CSRDirectAccessBundle
object CSRRegister {
// Refer to Spec. Vol.II Page 8-10
val MSTATUS = 0x300.U(Parameters.CSRRegisterAddrWidth)
val MIE = 0x304.U(Parameters.CSRRegisterAddrWidth)
val MTVEC = 0x305.U(Parameters.CSRRegisterAddrWidth)
val MSCRATCH = 0x340.U(Parameters.CSRRegisterAddrWidth)
val MEPC = 0x341.U(Parameters.CSRRegisterAddrWidth)
val MCAUSE = 0x342.U(Parameters.CSRRegisterAddrWidth)
val CycleL = 0xc00.U(Parameters.CSRRegisterAddrWidth)
val CycleH = 0xc80.U(Parameters.CSRRegisterAddrWidth)
}
class CSR extends Module {
val io = IO(new Bundle {
val reg_read_address_id = Input(UInt(Parameters.CSRRegisterAddrWidth))
val reg_write_enable_ex = Input(Bool())
val reg_write_address_ex = Input(UInt(Parameters.CSRRegisterAddrWidth))
val reg_write_data_ex = Input(UInt(Parameters.DataWidth))
val id_reg_read_data = Output(UInt(Parameters.DataWidth))
val clint_access_bundle = Flipped(new CSRDirectAccessBundle)
})
val mstatus = RegInit(UInt(Parameters.DataWidth), 0.U)
val mie = RegInit(UInt(Parameters.DataWidth), 0.U)
val mtvec = RegInit(UInt(Parameters.DataWidth), 0.U)
val mscratch = RegInit(UInt(Parameters.DataWidth), 0.U)
val mepc = RegInit(UInt(Parameters.DataWidth), 0.U)
val mcause = RegInit(UInt(Parameters.DataWidth), 0.U)
val cycles = RegInit(UInt(64.W), 0.U)
val regLUT =
IndexedSeq(
CSRRegister.MSTATUS -> mstatus,
CSRRegister.MIE -> mie,
CSRRegister.MTVEC -> mtvec,
CSRRegister.MSCRATCH -> mscratch,
CSRRegister.MEPC -> mepc,
CSRRegister.MCAUSE -> mcause,
CSRRegister.CycleL -> cycles(31, 0),
CSRRegister.CycleH -> cycles(63, 32),
)
cycles := cycles + 1.U
// If the pipeline and the CLINT are going to read and write the CSR at the same time, let the pipeline write first.
// This is implemented in a single cycle by passing reg_write_data_ex to clint and writing the data from the CLINT to the CSR.
io.id_reg_read_data := MuxLookup(io.reg_read_address_id, 0.U, regLUT)
io.clint_access_bundle.mstatus := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MSTATUS, io.reg_write_data_ex, mstatus)
io.clint_access_bundle.mtvec := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MTVEC, io.reg_write_data_ex, mtvec)
io.clint_access_bundle.mcause := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MCAUSE, io.reg_write_data_ex, mcause)
io.clint_access_bundle.mepc := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MEPC, io.reg_write_data_ex, mepc)
when(io.clint_access_bundle.direct_write_enable) {
mstatus := io.clint_access_bundle.mstatus_write_data
mepc := io.clint_access_bundle.mepc_write_data
mcause := io.clint_access_bundle.mcause_write_data
}.elsewhen(io.reg_write_enable_ex) {
when(io.reg_write_address_ex === CSRRegister.MSTATUS) {
mstatus := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_ex === CSRRegister.MEPC) {
mepc := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_ex === CSRRegister.MCAUSE) {
mcause := io.reg_write_data_ex
}
}
when(io.reg_write_enable_ex) {
when(io.reg_write_address_ex === CSRRegister.MIE) {
mie := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_ex === CSRRegister.MTVEC) {
mtvec := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_ex === CSRRegister.MSCRATCH) {
mscratch := io.reg_write_data_ex
}
}
}

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lab3/src/main/scala/riscv/core/PipelineRegister.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import riscv.Parameters
class PipelineRegister(width: Int = Parameters.DataBits, defaultValue: UInt = 0.U) extends Module {
val io = IO(new Bundle {
val stall = Input(Bool())
val flush = Input(Bool())
val in = Input(UInt(width.W))
val out = Output(UInt(width.W))
})
// Lab3(PipelineRegister)
io.out := 0.U
// Lab3(PipelineRegister) End
}

78
lab3/src/main/scala/riscv/core/RegisterFile.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core
import chisel3._
import chisel3.util._
import riscv.Parameters
object Registers extends Enumeration {
type Register = Value
val zero,
ra, sp, gp, tp,
t0, t1, t2, fp,
s1,
a0, a1, a2, a3, a4, a5, a6, a7,
s2, s3, s4, s5, s6, s7, s8, s9, s10, s11,
t3, t4, t5, t6 = Value
}
class RegisterFile extends Module {
val io = IO(new Bundle {
val write_enable = Input(Bool())
val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val write_data = Input(UInt(Parameters.DataWidth))
val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val read_data1 = Output(UInt(Parameters.DataWidth))
val read_data2 = Output(UInt(Parameters.DataWidth))
val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val debug_read_data = Output(UInt(Parameters.DataWidth))
})
val registers = Reg(Vec(Parameters.PhysicalRegisters, UInt(Parameters.DataWidth)))
when(!reset.asBool) {
when(io.write_enable && io.write_address =/= 0.U) {
registers(io.write_address) := io.write_data
}
}
io.read_data1 := MuxCase(
registers(io.read_address1),
IndexedSeq(
(io.read_address1 === 0.U) -> 0.U,
(io.read_address1 === io.write_address && io.write_enable) -> io.write_data
)
)
io.read_data2 := MuxCase(
registers(io.read_address2),
IndexedSeq(
(io.read_address2 === 0.U) -> 0.U,
(io.read_address2 === io.write_address && io.write_enable) -> io.write_data
)
)
io.debug_read_data := MuxCase(
registers(io.debug_read_address),
IndexedSeq(
(io.debug_read_address === 0.U) -> 0.U,
(io.debug_read_address === io.write_address && io.write_enable) -> io.write_data
)
)
}

101
lab3/src/main/scala/riscv/core/fivestage_final/CLINT.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util.MuxLookup
import riscv.Parameters
object InterruptStatus {
val None = 0x0.U(8.W)
val Timer0 = 0x1.U(8.W)
val Ret = 0xFF.U(8.W)
}
class CSRDirectAccessBundle extends Bundle {
val mstatus = Input(UInt(Parameters.DataWidth))
val mepc = Input(UInt(Parameters.DataWidth))
val mcause = Input(UInt(Parameters.DataWidth))
val mtvec = Input(UInt(Parameters.DataWidth))
val mstatus_write_data = Output(UInt(Parameters.DataWidth))
val mepc_write_data = Output(UInt(Parameters.DataWidth))
val mcause_write_data = Output(UInt(Parameters.DataWidth))
val direct_write_enable = Output(Bool())
}
// Core Local Interrupt Controller
class CLINT extends Module {
val io = IO(new Bundle {
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val instruction_id = Input(UInt(Parameters.InstructionWidth))
val instruction_address_if = Input(UInt(Parameters.AddrWidth))
val jump_flag = Input(Bool())
val jump_address = Input(UInt(Parameters.AddrWidth))
val id_interrupt_handler_address = Output(UInt(Parameters.AddrWidth))
val id_interrupt_assert = Output(Bool())
val csr_bundle = new CSRDirectAccessBundle
})
val interrupt_enable = io.csr_bundle.mstatus(3)
val instruction_address = Mux(
io.jump_flag,
io.jump_address,
io.instruction_address_if,
)
val mstatus_disable_interrupt = io.csr_bundle.mstatus(31, 4) ## 0.U(1.W) ## io.csr_bundle.mstatus(2, 0)
val mstatus_recover_interrupt = io.csr_bundle.mstatus(31, 4) ## io.csr_bundle.mstatus(7) ## io.csr_bundle.mstatus(2, 0)
when(io.instruction_id === InstructionsEnv.ecall || io.instruction_id === InstructionsEnv.ebreak) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := MuxLookup(
io.instruction_id,
10.U,
IndexedSeq(
InstructionsEnv.ecall -> 11.U,
InstructionsEnv.ebreak -> 3.U,
)
)
io.csr_bundle.direct_write_enable := true.B
io.id_interrupt_assert := true.B
io.id_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.interrupt_flag =/= InterruptStatus.None && interrupt_enable) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := Mux(io.interrupt_flag(0), 0x80000007L.U, 0x8000000BL.U)
io.csr_bundle.direct_write_enable := true.B
io.id_interrupt_assert := true.B
io.id_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.instruction_id === InstructionsRet.mret) {
io.csr_bundle.mstatus_write_data := mstatus_recover_interrupt
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := true.B
io.id_interrupt_assert := true.B
io.id_interrupt_handler_address := io.csr_bundle.mepc
}.otherwise {
io.csr_bundle.mstatus_write_data := io.csr_bundle.mstatus
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := false.B
io.id_interrupt_assert := false.B
io.id_interrupt_handler_address := 0.U
}
}

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lab3/src/main/scala/riscv/core/fivestage_final/CPU.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
import riscv.core.{CPUBundle, CSR, RegisterFile}
class CPU extends Module {
val io = IO(new CPUBundle)
val ctrl = Module(new Control)
val regs = Module(new RegisterFile)
val inst_fetch = Module(new InstructionFetch)
val if2id = Module(new IF2ID)
val id = Module(new InstructionDecode)
val id2ex = Module(new ID2EX)
val ex = Module(new Execute)
val ex2mem = Module(new EX2MEM)
val mem = Module(new MemoryAccess)
val mem2wb = Module(new MEM2WB)
val wb = Module(new WriteBack)
val forwarding = Module(new Forwarding)
val clint = Module(new CLINT)
val csr_regs = Module(new CSR)
ctrl.io.jump_flag := id.io.if_jump_flag
ctrl.io.jump_instruction_id := id.io.ctrl_jump_instruction
ctrl.io.rs1_id := id.io.regs_reg1_read_address
ctrl.io.rs2_id := id.io.regs_reg2_read_address
ctrl.io.memory_read_enable_ex := id2ex.io.output_memory_read_enable
ctrl.io.rd_ex := id2ex.io.output_regs_write_address
ctrl.io.memory_read_enable_mem := ex2mem.io.output_memory_read_enable
ctrl.io.rd_mem := ex2mem.io.output_regs_write_address
regs.io.write_enable := mem2wb.io.output_regs_write_enable
regs.io.write_address := mem2wb.io.output_regs_write_address
regs.io.write_data := wb.io.regs_write_data
regs.io.read_address1 := id.io.regs_reg1_read_address
regs.io.read_address2 := id.io.regs_reg2_read_address
regs.io.debug_read_address := io.debug_read_address
io.debug_read_data := regs.io.debug_read_data
io.instruction_address := inst_fetch.io.instruction_address
inst_fetch.io.stall_flag_ctrl := ctrl.io.pc_stall
inst_fetch.io.jump_flag_id := id.io.if_jump_flag
inst_fetch.io.jump_address_id := id.io.if_jump_address
inst_fetch.io.rom_instruction := io.instruction
inst_fetch.io.instruction_valid := io.instruction_valid
if2id.io.stall := ctrl.io.if_stall
if2id.io.flush := ctrl.io.if_flush
if2id.io.instruction := inst_fetch.io.id_instruction
if2id.io.instruction_address := inst_fetch.io.instruction_address
if2id.io.interrupt_flag := io.interrupt_flag
id.io.instruction := if2id.io.output_instruction
id.io.instruction_address := if2id.io.output_instruction_address
id.io.reg1_data := regs.io.read_data1
id.io.reg2_data := regs.io.read_data2
id.io.forward_from_mem := mem.io.forward_data
id.io.forward_from_wb := wb.io.regs_write_data
id.io.reg1_forward := forwarding.io.reg1_forward_id
id.io.reg2_forward := forwarding.io.reg2_forward_id
id.io.interrupt_assert := clint.io.id_interrupt_assert
id.io.interrupt_handler_address := clint.io.id_interrupt_handler_address
id2ex.io.flush := ctrl.io.id_flush
id2ex.io.instruction := if2id.io.output_instruction
id2ex.io.instruction_address := if2id.io.output_instruction_address
id2ex.io.reg1_data := regs.io.read_data1
id2ex.io.reg2_data := regs.io.read_data2
id2ex.io.regs_reg1_read_address := id.io.regs_reg1_read_address
id2ex.io.regs_reg2_read_address := id.io.regs_reg2_read_address
id2ex.io.regs_write_enable := id.io.ex_reg_write_enable
id2ex.io.regs_write_address := id.io.ex_reg_write_address
id2ex.io.regs_write_source := id.io.ex_reg_write_source
id2ex.io.immediate := id.io.ex_immediate
id2ex.io.aluop1_source := id.io.ex_aluop1_source
id2ex.io.aluop2_source := id.io.ex_aluop2_source
id2ex.io.csr_write_enable := id.io.ex_csr_write_enable
id2ex.io.csr_address := id.io.ex_csr_address
id2ex.io.memory_read_enable := id.io.ex_memory_read_enable
id2ex.io.memory_write_enable := id.io.ex_memory_write_enable
id2ex.io.csr_read_data := csr_regs.io.id_reg_read_data
ex.io.instruction := id2ex.io.output_instruction
ex.io.instruction_address := id2ex.io.output_instruction_address
ex.io.reg1_data := id2ex.io.output_reg1_data
ex.io.reg2_data := id2ex.io.output_reg2_data
ex.io.immediate := id2ex.io.output_immediate
ex.io.aluop1_source := id2ex.io.output_aluop1_source
ex.io.aluop2_source := id2ex.io.output_aluop2_source
ex.io.csr_read_data := id2ex.io.output_csr_read_data
ex.io.forward_from_mem := mem.io.forward_data
ex.io.forward_from_wb := wb.io.regs_write_data
ex.io.reg1_forward := forwarding.io.reg1_forward_ex
ex.io.reg2_forward := forwarding.io.reg2_forward_ex
ex2mem.io.regs_write_enable := id2ex.io.output_regs_write_enable
ex2mem.io.regs_write_source := id2ex.io.output_regs_write_source
ex2mem.io.regs_write_address := id2ex.io.output_regs_write_address
ex2mem.io.instruction_address := id2ex.io.output_instruction_address
ex2mem.io.funct3 := id2ex.io.output_instruction(14, 12)
ex2mem.io.reg2_data := ex.io.mem_reg2_data
ex2mem.io.memory_read_enable := id2ex.io.output_memory_read_enable
ex2mem.io.memory_write_enable := id2ex.io.output_memory_write_enable
ex2mem.io.alu_result := ex.io.mem_alu_result
ex2mem.io.csr_read_data := id2ex.io.output_csr_read_data
mem.io.alu_result := ex2mem.io.output_alu_result
mem.io.reg2_data := ex2mem.io.output_reg2_data
mem.io.memory_read_enable := ex2mem.io.output_memory_read_enable
mem.io.memory_write_enable := ex2mem.io.output_memory_write_enable
mem.io.funct3 := ex2mem.io.output_funct3
mem.io.regs_write_source := ex2mem.io.output_regs_write_source
mem.io.csr_read_data := ex2mem.io.output_csr_read_data
io.device_select := mem.io.bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
io.memory_bundle <> mem.io.bundle
io.memory_bundle.address := 0.U(Parameters.SlaveDeviceCountBits.W) ## mem.io.bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0)
mem2wb.io.instruction_address := ex2mem.io.output_instruction_address
mem2wb.io.alu_result := ex2mem.io.output_alu_result
mem2wb.io.regs_write_enable := ex2mem.io.output_regs_write_enable
mem2wb.io.regs_write_source := ex2mem.io.output_regs_write_source
mem2wb.io.regs_write_address := ex2mem.io.output_regs_write_address
mem2wb.io.memory_read_data := mem.io.wb_memory_read_data
mem2wb.io.csr_read_data := ex2mem.io.output_csr_read_data
wb.io.instruction_address := mem2wb.io.output_instruction_address
wb.io.alu_result := mem2wb.io.output_alu_result
wb.io.memory_read_data := mem2wb.io.output_memory_read_data
wb.io.regs_write_source := mem2wb.io.output_regs_write_source
wb.io.csr_read_data := mem2wb.io.output_csr_read_data
forwarding.io.rs1_id := id.io.regs_reg1_read_address
forwarding.io.rs2_id := id.io.regs_reg2_read_address
forwarding.io.rs1_ex := id2ex.io.output_regs_reg1_read_address
forwarding.io.rs2_ex := id2ex.io.output_regs_reg2_read_address
forwarding.io.rd_mem := ex2mem.io.output_regs_write_address
forwarding.io.reg_write_enable_mem := ex2mem.io.output_regs_write_enable
forwarding.io.rd_wb := mem2wb.io.output_regs_write_address
forwarding.io.reg_write_enable_wb := mem2wb.io.output_regs_write_enable
clint.io.instruction_address_if := inst_fetch.io.instruction_address
clint.io.instruction_id := if2id.io.output_instruction
clint.io.jump_flag := id.io.clint_jump_flag
clint.io.jump_address := id.io.clint_jump_address
clint.io.interrupt_flag := if2id.io.output_interrupt_flag
clint.io.csr_bundle <> csr_regs.io.clint_access_bundle
csr_regs.io.reg_read_address_id := id.io.ex_csr_address
csr_regs.io.reg_write_enable_ex := id2ex.io.output_csr_write_enable
csr_regs.io.reg_write_address_ex := id2ex.io.output_csr_address
csr_regs.io.reg_write_data_ex := ex.io.csr_write_data
}

43
lab3/src/main/scala/riscv/core/fivestage_final/Control.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
class Control extends Module {
val io = IO(new Bundle {
val jump_flag = Input(Bool())
val jump_instruction_id = Input(Bool())
val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val memory_read_enable_ex = Input(Bool())
val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val memory_read_enable_mem = Input(Bool())
val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val if_flush = Output(Bool())
val id_flush = Output(Bool())
val pc_stall = Output(Bool())
val if_stall = Output(Bool())
})
// Lab3(Final)
io.if_flush := false.B
io.id_flush := false.B
io.pc_stall := false.B
io.if_stall := false.B
// Lab3(Final) End
}

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lab3/src/main/scala/riscv/core/fivestage_final/EX2MEM.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class EX2MEM extends Module {
val io = IO(new Bundle() {
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val funct3 = Input(UInt(3.W))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val alu_result = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_funct3 = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.AddrBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val funct3 = Module(new PipelineRegister(3))
funct3.io.in := io.funct3
funct3.io.stall := stall
funct3.io.flush := flush
io.output_funct3 := funct3.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := flush
io.output_reg2_data := reg2_data.io.out
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

93
lab3/src/main/scala/riscv/core/fivestage_final/Execute.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util._
import riscv.Parameters
import riscv.core.{ALU, ALUControl}
class Execute extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate = Input(UInt(Parameters.DataWidth))
val aluop1_source = Input(UInt(1.W))
val aluop2_source = Input(UInt(1.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val forward_from_mem = Input(UInt(Parameters.DataWidth))
val forward_from_wb = Input(UInt(Parameters.DataWidth))
val reg1_forward = Input(UInt(2.W))
val reg2_forward = Input(UInt(2.W))
val mem_alu_result = Output(UInt(Parameters.DataWidth))
val mem_reg2_data = Output(UInt(Parameters.DataWidth))
val csr_write_data = Output(UInt(Parameters.DataWidth))
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val uimm = io.instruction(19, 15)
val alu = Module(new ALU)
val alu_ctrl = Module(new ALUControl)
alu_ctrl.io.opcode := opcode
alu_ctrl.io.funct3 := funct3
alu_ctrl.io.funct7 := funct7
alu.io.func := alu_ctrl.io.alu_funct
val reg1_data = MuxLookup(
io.reg1_forward,
io.reg1_data,
IndexedSeq(
ForwardingType.ForwardFromMEM -> io.forward_from_mem,
ForwardingType.ForwardFromWB -> io.forward_from_wb
)
)
alu.io.op1 := Mux(
io.aluop1_source === ALUOp1Source.InstructionAddress,
io.instruction_address,
reg1_data
)
val reg2_data = MuxLookup(
io.reg2_forward,
io.reg2_data,
IndexedSeq(
ForwardingType.ForwardFromMEM -> io.forward_from_mem,
ForwardingType.ForwardFromWB -> io.forward_from_wb
)
)
alu.io.op2 := Mux(
io.aluop2_source === ALUOp2Source.Immediate,
io.immediate,
reg2_data
)
io.mem_alu_result := alu.io.result
io.mem_reg2_data := reg2_data
io.csr_write_data := MuxLookup(funct3, 0.U, IndexedSeq(
InstructionsTypeCSR.csrrw -> reg1_data,
InstructionsTypeCSR.csrrc -> io.csr_read_data.&((~reg1_data).asUInt),
InstructionsTypeCSR.csrrs -> io.csr_read_data.|(reg1_data),
InstructionsTypeCSR.csrrwi -> Cat(0.U(27.W), uimm),
InstructionsTypeCSR.csrrci -> io.csr_read_data.&((~Cat(0.U(27.W), uimm)).asUInt),
InstructionsTypeCSR.csrrsi -> io.csr_read_data.|(Cat(0.U(27.W), uimm)),
))
}

49
lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
object ForwardingType {
val NoForward = 0.U(2.W)
val ForwardFromMEM = 1.U(2.W)
val ForwardFromWB = 2.U(2.W)
}
class Forwarding extends Module {
val io = IO(new Bundle() {
val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs1_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_mem = Input(Bool())
val rd_wb = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_wb = Input(Bool())
val reg1_forward_id = Output(UInt(2.W))
val reg2_forward_id = Output(UInt(2.W))
val reg1_forward_ex = Output(UInt(2.W))
val reg2_forward_ex = Output(UInt(2.W))
})
// Lab3(Final)
io.reg1_forward_id := 0.U
io.reg2_forward_id := 0.U
io.reg1_forward_ex := 0.U
io.reg2_forward_ex := 0.U
// Lab3(Final) End
}

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lab3/src/main/scala/riscv/core/fivestage_final/ID2EX.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class ID2EX extends Module {
val io = IO(new Bundle {
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val regs_reg1_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_enable = Input(Bool())
val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_source = Input(UInt(2.W))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate = Input(UInt(Parameters.DataWidth))
val aluop1_source = Input(UInt(1.W))
val aluop2_source = Input(UInt(1.W))
val csr_write_enable = Input(Bool())
val csr_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_source = Output(UInt(2.W))
val output_reg1_data = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_immediate = Output(UInt(Parameters.DataWidth))
val output_aluop1_source = Output(UInt(1.W))
val output_aluop2_source = Output(UInt(1.W))
val output_csr_write_enable = Output(Bool())
val output_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val regs_reg1_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg1_read_address.io.in := io.regs_reg1_read_address
regs_reg1_read_address.io.stall := stall
regs_reg1_read_address.io.flush := io.flush
io.output_regs_reg1_read_address := regs_reg1_read_address.io.out
val regs_reg2_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg2_read_address.io.in := io.regs_reg2_read_address
regs_reg2_read_address.io.stall := stall
regs_reg2_read_address.io.flush := io.flush
io.output_regs_reg2_read_address := regs_reg2_read_address.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := io.flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := io.flush
io.output_regs_write_address := regs_write_address.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := io.flush
io.output_regs_write_source := regs_write_source.io.out
val reg1_data = Module(new PipelineRegister())
reg1_data.io.in := io.reg1_data
reg1_data.io.stall := stall
reg1_data.io.flush := io.flush
io.output_reg1_data := reg1_data.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := io.flush
io.output_reg2_data := reg2_data.io.out
val immediate = Module(new PipelineRegister())
immediate.io.in := io.immediate
immediate.io.stall := stall
immediate.io.flush := io.flush
io.output_immediate := immediate.io.out
val aluop1_source = Module(new PipelineRegister(1))
aluop1_source.io.in := io.aluop1_source
aluop1_source.io.stall := stall
aluop1_source.io.flush := io.flush
io.output_aluop1_source := aluop1_source.io.out
val aluop2_source = Module(new PipelineRegister(1))
aluop2_source.io.in := io.aluop2_source
aluop2_source.io.stall := stall
aluop2_source.io.flush := io.flush
io.output_aluop2_source := aluop2_source.io.out
val csr_write_enable = Module(new PipelineRegister(1))
csr_write_enable.io.in := io.csr_write_enable
csr_write_enable.io.stall := stall
csr_write_enable.io.flush := io.flush
io.output_csr_write_enable := csr_write_enable.io.out
val csr_address = Module(new PipelineRegister(Parameters.CSRRegisterAddrBits))
csr_address.io.in := io.csr_address
csr_address.io.stall := stall
csr_address.io.flush := io.flush
io.output_csr_address := csr_address.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := io.flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := io.flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := io.flush
io.output_csr_read_data := csr_read_data.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_final/IF2ID.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class IF2ID extends Module {
val io = IO(new Bundle {
val stall = Input(Bool())
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth))
})
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := io.stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := io.stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val interrupt_flag = Module(new PipelineRegister(Parameters.InterruptFlagBits))
interrupt_flag.io.in := io.interrupt_flag
interrupt_flag.io.stall := io.stall
interrupt_flag.io.flush := io.flush
io.output_interrupt_flag := interrupt_flag.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_final/InstructionDecode.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util._
import riscv.Parameters
object InstructionTypes {
val L = "b0000011".U
val I = "b0010011".U
val S = "b0100011".U
val RM = "b0110011".U
val B = "b1100011".U
}
object Instructions {
val lui = "b0110111".U
val nop = "b0000001".U
val jal = "b1101111".U
val jalr = "b1100111".U
val auipc = "b0010111".U
val csr = "b1110011".U
val fence = "b0001111".U
}
object InstructionsTypeL {
val lb = "b000".U
val lh = "b001".U
val lw = "b010".U
val lbu = "b100".U
val lhu = "b101".U
}
object InstructionsTypeI {
val addi = 0.U
val slli = 1.U
val slti = 2.U
val sltiu = 3.U
val xori = 4.U
val sri = 5.U
val ori = 6.U
val andi = 7.U
}
object InstructionsTypeS {
val sb = "b000".U
val sh = "b001".U
val sw = "b010".U
}
object InstructionsTypeR {
val add_sub = 0.U
val sll = 1.U
val slt = 2.U
val sltu = 3.U
val xor = 4.U
val sr = 5.U
val or = 6.U
val and = 7.U
}
object InstructionsTypeM {
val mul = 0.U
val mulh = 1.U
val mulhsu = 2.U
val mulhum = 3.U
val div = 4.U
val divu = 5.U
val rem = 6.U
val remu = 7.U
}
object InstructionsTypeB {
val beq = "b000".U
val bne = "b001".U
val blt = "b100".U
val bge = "b101".U
val bltu = "b110".U
val bgeu = "b111".U
}
object InstructionsTypeCSR {
val csrrw = "b001".U
val csrrs = "b010".U
val csrrc = "b011".U
val csrrwi = "b101".U
val csrrsi = "b110".U
val csrrci = "b111".U
}
object InstructionsNop {
val nop = 0x00000013L.U(Parameters.DataWidth)
}
object InstructionsRet {
val mret = 0x30200073L.U(Parameters.DataWidth)
val ret = 0x00008067L.U(Parameters.DataWidth)
}
object InstructionsEnv {
val ecall = 0x00000073L.U(Parameters.DataWidth)
val ebreak = 0x00100073L.U(Parameters.DataWidth)
}
object ALUOp1Source {
val Register = 0.U(1.W)
val InstructionAddress = 1.U(1.W)
}
object ALUOp2Source {
val Register = 0.U(1.W)
val Immediate = 1.U(1.W)
}
object RegWriteSource {
val ALUResult = 0.U(2.W)
val Memory = 1.U(2.W)
val CSR = 2.U(2.W)
val NextInstructionAddress = 3.U(2.W)
}
class InstructionDecode extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val forward_from_mem = Input(UInt(Parameters.DataWidth))
val forward_from_wb = Input(UInt(Parameters.DataWidth))
val reg1_forward = Input(UInt(2.W))
val reg2_forward = Input(UInt(2.W))
val interrupt_assert = Input(Bool())
val interrupt_handler_address = Input(UInt(Parameters.AddrWidth))
val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_immediate = Output(UInt(Parameters.DataWidth))
val ex_aluop1_source = Output(UInt(1.W))
val ex_aluop2_source = Output(UInt(1.W))
val ex_memory_read_enable = Output(Bool())
val ex_memory_write_enable = Output(Bool())
val ex_reg_write_source = Output(UInt(2.W))
val ex_reg_write_enable = Output(Bool())
val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val ex_csr_write_enable = Output(Bool())
val ctrl_jump_instruction = Output(Bool())
val clint_jump_flag = Output(Bool())
val clint_jump_address = Output(UInt(Parameters.AddrWidth))
val if_jump_flag = Output(Bool())
val if_jump_address = Output(UInt(Parameters.AddrWidth))
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val rd = io.instruction(11, 7)
val rs1 = io.instruction(19, 15)
val rs2 = io.instruction(24, 20)
io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
io.regs_reg2_read_address := rs2
io.ex_immediate := MuxLookup(
opcode,
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
IndexedSeq(
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
)
)
io.ex_aluop1_source := Mux(
opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
ALUOp1Source.InstructionAddress,
ALUOp1Source.Register
)
io.ex_aluop2_source := Mux(
opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
io.ex_memory_read_enable := opcode === InstructionTypes.L
io.ex_memory_write_enable := opcode === InstructionTypes.S
io.ex_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult,
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.csr -> RegWriteSource.CSR,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)
io.ex_reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
(opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr)
io.ex_reg_write_address := io.instruction(11, 7)
io.ex_csr_address := io.instruction(31, 20)
io.ex_csr_write_enable := (opcode === Instructions.csr) && (
funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi ||
funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi ||
funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci
)
// Lab3(Final)
io.ctrl_jump_instruction := false.B
io.clint_jump_flag := false.B
io.clint_jump_address := 0.U
io.if_jump_flag := false.B
io.if_jump_address := 0.U
// Lab3(Final) End
}

48
lab3/src/main/scala/riscv/core/fivestage_final/InstructionFetch.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util.MuxCase
import riscv.Parameters
object ProgramCounter {
val EntryAddress = Parameters.EntryAddress
}
class InstructionFetch extends Module {
val io = IO(new Bundle {
val stall_flag_ctrl = Input(Bool())
val jump_flag_id = Input(Bool())
val jump_address_id = Input(UInt(Parameters.AddrWidth))
val rom_instruction = Input(UInt(Parameters.DataWidth))
val instruction_valid = Input(Bool())
val instruction_address = Output(UInt(Parameters.AddrWidth))
val id_instruction = Output(UInt(Parameters.InstructionWidth))
})
val pc = RegInit(ProgramCounter.EntryAddress)
pc := MuxCase(
pc + 4.U,
IndexedSeq(
(io.jump_flag_id && !io.stall_flag_ctrl) -> io.jump_address_id,
(io.stall_flag_ctrl || !io.instruction_valid) -> pc
)
)
io.instruction_address := pc
io.id_instruction := Mux(io.instruction_valid, io.rom_instruction, InstructionsNop.nop)
}

83
lab3/src/main/scala/riscv/core/fivestage_final/MEM2WB.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class MEM2WB extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_memory_read_data = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_data = Module(new PipelineRegister())
memory_read_data.io.in := io.memory_read_data
memory_read_data.io.stall := stall
memory_read_data.io.flush := flush
io.output_memory_read_data := memory_read_data.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.InstructionBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_final/MemoryAccess.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util._
import peripheral.RAMBundle
import riscv.Parameters
class MemoryAccess extends Module {
val io = IO(new Bundle() {
val alu_result = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val funct3 = Input(UInt(3.W))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
val forward_data = Output(UInt(Parameters.DataWidth))
val bundle = Flipped(new RAMBundle)
})
val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
io.bundle.write_enable := io.memory_write_enable
io.bundle.write_data := 0.U
io.bundle.address := io.alu_result
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
io.wb_memory_read_data := 0.U
when(io.memory_read_enable) {
val data = io.bundle.read_data
io.wb_memory_read_data := MuxLookup(
io.funct3,
0.U,
IndexedSeq(
InstructionsTypeL.lb -> MuxLookup(
mem_address_index,
Cat(Fill(24, data(31)), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
2.U -> Cat(Fill(24, data(23)), data(23, 16))
)
),
InstructionsTypeL.lbu -> MuxLookup(
mem_address_index,
Cat(Fill(24, 0.U), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
2.U -> Cat(Fill(24, 0.U), data(23, 16))
)
),
InstructionsTypeL.lh -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, data(15)), data(15, 0)),
Cat(Fill(16, data(31)), data(31, 16))
),
InstructionsTypeL.lhu -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, 0.U), data(15, 0)),
Cat(Fill(16, 0.U), data(31, 16))
),
InstructionsTypeL.lw -> data
)
)
}.elsewhen(io.memory_write_enable) {
io.bundle.write_data := io.reg2_data
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
when(io.funct3 === InstructionsTypeS.sb) {
io.bundle.write_strobe(mem_address_index) := true.B
io.bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
}.elsewhen(io.funct3 === InstructionsTypeS.sh) {
when(mem_address_index === 0.U) {
for (i <- 0 until Parameters.WordSize / 2) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
}.otherwise {
for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
.WordSize / 2 * Parameters.ByteBits)
}
}.elsewhen(io.funct3 === InstructionsTypeS.sw) {
for (i <- 0 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
}
}
io.forward_data := Mux(io.regs_write_source === RegWriteSource.CSR, io.csr_read_data, io.alu_result)
}

40
lab3/src/main/scala/riscv/core/fivestage_final/WriteBack.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_final
import chisel3._
import chisel3.util._
import riscv.Parameters
class WriteBack extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_data = Output(UInt(Parameters.DataWidth))
})
io.regs_write_data := MuxLookup(
io.regs_write_source,
io.alu_result,
IndexedSeq(
RegWriteSource.Memory -> io.memory_read_data,
RegWriteSource.CSR -> io.csr_read_data,
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
)
)
}

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lab3/src/main/scala/riscv/core/fivestage_forward/CLINT.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util.MuxLookup
import riscv.Parameters
object InterruptStatus {
val None = 0x0.U(8.W)
val Timer0 = 0x1.U(8.W)
val Ret = 0xFF.U(8.W)
}
class CSRDirectAccessBundle extends Bundle {
val mstatus = Input(UInt(Parameters.DataWidth))
val mepc = Input(UInt(Parameters.DataWidth))
val mcause = Input(UInt(Parameters.DataWidth))
val mtvec = Input(UInt(Parameters.DataWidth))
val mstatus_write_data = Output(UInt(Parameters.DataWidth))
val mepc_write_data = Output(UInt(Parameters.DataWidth))
val mcause_write_data = Output(UInt(Parameters.DataWidth))
val direct_write_enable = Output(Bool())
}
// Core Local Interrupt Controller
class CLINT extends Module {
val io = IO(new Bundle {
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val instruction_ex = Input(UInt(Parameters.InstructionWidth))
val instruction_address_if = Input(UInt(Parameters.AddrWidth))
val instruction_address_id = Input(UInt(Parameters.AddrWidth))
val jump_flag = Input(Bool())
val jump_address = Input(UInt(Parameters.AddrWidth))
val ex_interrupt_handler_address = Output(UInt(Parameters.AddrWidth))
val ex_interrupt_assert = Output(Bool())
val csr_bundle = new CSRDirectAccessBundle
})
val interrupt_enable = io.csr_bundle.mstatus(3)
val jumpping = RegNext(io.jump_flag || io.ex_interrupt_assert)
val instruction_address = Mux(
io.jump_flag,
io.jump_address,
Mux(jumpping, io.instruction_address_if, io.instruction_address_id)
)
val mstatus_disable_interrupt = io.csr_bundle.mstatus(31, 4) ## 0.U(1.W) ## io.csr_bundle.mstatus(2, 0)
val mstatus_recover_interrupt = io.csr_bundle.mstatus(31, 4) ## io.csr_bundle.mstatus(7) ## io.csr_bundle.mstatus(2, 0)
when(io.instruction_ex === InstructionsEnv.ecall || io.instruction_ex === InstructionsEnv.ebreak) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := MuxLookup(
io.instruction_ex,
10.U,
IndexedSeq(
InstructionsEnv.ecall -> 11.U,
InstructionsEnv.ebreak -> 3.U,
)
)
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.interrupt_flag =/= InterruptStatus.None && interrupt_enable) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := Mux(io.interrupt_flag(0), 0x80000007L.U, 0x8000000BL.U)
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.instruction_ex === InstructionsRet.mret) {
io.csr_bundle.mstatus_write_data := mstatus_recover_interrupt
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mepc
}.otherwise {
io.csr_bundle.mstatus_write_data := io.csr_bundle.mstatus
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := false.B
io.ex_interrupt_assert := false.B
io.ex_interrupt_handler_address := 0.U
}
}

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lab3/src/main/scala/riscv/core/fivestage_forward/CPU.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
import riscv.core.{CPUBundle, CSR, RegisterFile}
class CPU extends Module {
val io = IO(new CPUBundle)
val ctrl = Module(new Control)
val regs = Module(new RegisterFile)
val inst_fetch = Module(new InstructionFetch)
val if2id = Module(new IF2ID)
val id = Module(new InstructionDecode)
val id2ex = Module(new ID2EX)
val ex = Module(new Execute)
val ex2mem = Module(new EX2MEM)
val mem = Module(new MemoryAccess)
val mem2wb = Module(new MEM2WB)
val wb = Module(new WriteBack)
val forwarding = Module(new Forwarding)
val clint = Module(new CLINT)
val csr_regs = Module(new CSR)
ctrl.io.jump_flag := ex.io.if_jump_flag
ctrl.io.rs1_id := id.io.regs_reg1_read_address
ctrl.io.rs2_id := id.io.regs_reg2_read_address
ctrl.io.memory_read_enable_ex := id2ex.io.output_memory_read_enable
ctrl.io.rd_ex := id2ex.io.output_regs_write_address
regs.io.write_enable := mem2wb.io.output_regs_write_enable
regs.io.write_address := mem2wb.io.output_regs_write_address
regs.io.write_data := wb.io.regs_write_data
regs.io.read_address1 := id.io.regs_reg1_read_address
regs.io.read_address2 := id.io.regs_reg2_read_address
regs.io.debug_read_address := io.debug_read_address
io.debug_read_data := regs.io.debug_read_data
io.instruction_address := inst_fetch.io.instruction_address
inst_fetch.io.stall_flag_ctrl := ctrl.io.pc_stall
inst_fetch.io.jump_flag_id := ex.io.if_jump_flag
inst_fetch.io.jump_address_id := ex.io.if_jump_address
inst_fetch.io.rom_instruction := io.instruction
inst_fetch.io.instruction_valid := io.instruction_valid
if2id.io.stall := ctrl.io.if_stall
if2id.io.flush := ctrl.io.if_flush
if2id.io.instruction := inst_fetch.io.id_instruction
if2id.io.instruction_address := inst_fetch.io.instruction_address
if2id.io.interrupt_flag := io.interrupt_flag
id.io.instruction := if2id.io.output_instruction
id2ex.io.flush := ctrl.io.id_flush
id2ex.io.instruction := if2id.io.output_instruction
id2ex.io.instruction_address := if2id.io.output_instruction_address
id2ex.io.reg1_data := regs.io.read_data1
id2ex.io.reg2_data := regs.io.read_data2
id2ex.io.regs_reg1_read_address := id.io.regs_reg1_read_address
id2ex.io.regs_reg2_read_address := id.io.regs_reg2_read_address
id2ex.io.regs_write_enable := id.io.ex_reg_write_enable
id2ex.io.regs_write_address := id.io.ex_reg_write_address
id2ex.io.regs_write_source := id.io.ex_reg_write_source
id2ex.io.immediate := id.io.ex_immediate
id2ex.io.aluop1_source := id.io.ex_aluop1_source
id2ex.io.aluop2_source := id.io.ex_aluop2_source
id2ex.io.csr_write_enable := id.io.ex_csr_write_enable
id2ex.io.csr_address := id.io.ex_csr_address
id2ex.io.memory_read_enable := id.io.ex_memory_read_enable
id2ex.io.memory_write_enable := id.io.ex_memory_write_enable
id2ex.io.csr_read_data := csr_regs.io.id_reg_read_data
ex.io.instruction := id2ex.io.output_instruction
ex.io.instruction_address := id2ex.io.output_instruction_address
ex.io.reg1_data := id2ex.io.output_reg1_data
ex.io.reg2_data := id2ex.io.output_reg2_data
ex.io.immediate_id := id2ex.io.output_immediate
ex.io.aluop1_source_id := id2ex.io.output_aluop1_source
ex.io.aluop2_source_id := id2ex.io.output_aluop2_source
ex.io.csr_read_data_id := id2ex.io.output_csr_read_data
ex.io.forward_from_mem := mem.io.forward_data
ex.io.forward_from_wb := wb.io.regs_write_data
ex.io.reg1_forward := forwarding.io.reg1_forward_ex
ex.io.reg2_forward := forwarding.io.reg2_forward_ex
ex.io.interrupt_assert_clint := clint.io.ex_interrupt_assert
ex.io.interrupt_handler_address_clint := clint.io.ex_interrupt_handler_address
ex2mem.io.regs_write_enable := id2ex.io.output_regs_write_enable
ex2mem.io.regs_write_source := id2ex.io.output_regs_write_source
ex2mem.io.regs_write_address := id2ex.io.output_regs_write_address
ex2mem.io.instruction_address := id2ex.io.output_instruction_address
ex2mem.io.funct3 := id2ex.io.output_instruction(14, 12)
ex2mem.io.reg2_data := ex.io.mem_reg2_data
ex2mem.io.memory_read_enable := id2ex.io.output_memory_read_enable
ex2mem.io.memory_write_enable := id2ex.io.output_memory_write_enable
ex2mem.io.alu_result := ex.io.mem_alu_result
ex2mem.io.csr_read_data := id2ex.io.output_csr_read_data
mem.io.alu_result := ex2mem.io.output_alu_result
mem.io.reg2_data := ex2mem.io.output_reg2_data
mem.io.memory_read_enable := ex2mem.io.output_memory_read_enable
mem.io.memory_write_enable := ex2mem.io.output_memory_write_enable
mem.io.funct3 := ex2mem.io.output_funct3
mem.io.regs_write_source := ex2mem.io.output_regs_write_source
mem.io.csr_read_data := ex2mem.io.output_csr_read_data
io.device_select := mem.io.bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
io.memory_bundle <> mem.io.bundle
io.memory_bundle.address := 0.U(Parameters.SlaveDeviceCountBits.W) ## mem.io.bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0)
mem2wb.io.instruction_address := ex2mem.io.output_instruction_address
mem2wb.io.alu_result := ex2mem.io.output_alu_result
mem2wb.io.regs_write_enable := ex2mem.io.output_regs_write_enable
mem2wb.io.regs_write_source := ex2mem.io.output_regs_write_source
mem2wb.io.regs_write_address := ex2mem.io.output_regs_write_address
mem2wb.io.memory_read_data := mem.io.wb_memory_read_data
mem2wb.io.csr_read_data := ex2mem.io.output_csr_read_data
wb.io.instruction_address := mem2wb.io.output_instruction_address
wb.io.alu_result := mem2wb.io.output_alu_result
wb.io.memory_read_data := mem2wb.io.output_memory_read_data
wb.io.regs_write_source := mem2wb.io.output_regs_write_source
wb.io.csr_read_data := mem2wb.io.output_csr_read_data
forwarding.io.rs1_ex := id2ex.io.output_regs_reg1_read_address
forwarding.io.rs2_ex := id2ex.io.output_regs_reg2_read_address
forwarding.io.rd_mem := ex2mem.io.output_regs_write_address
forwarding.io.reg_write_enable_mem := ex2mem.io.output_regs_write_enable
forwarding.io.rd_wb := mem2wb.io.output_regs_write_address
forwarding.io.reg_write_enable_wb := mem2wb.io.output_regs_write_enable
clint.io.instruction_address_if := inst_fetch.io.instruction_address
clint.io.instruction_address_id := if2id.io.output_instruction_address
clint.io.instruction_ex := id2ex.io.output_instruction
clint.io.jump_flag := ex.io.clint_jump_flag
clint.io.jump_address := ex.io.clint_jump_address
clint.io.interrupt_flag := if2id.io.output_interrupt_flag
clint.io.csr_bundle <> csr_regs.io.clint_access_bundle
csr_regs.io.reg_read_address_id := id.io.ex_csr_address
csr_regs.io.reg_write_enable_ex := id2ex.io.output_csr_write_enable
csr_regs.io.reg_write_address_ex := id2ex.io.output_csr_address
csr_regs.io.reg_write_data_ex := ex.io.csr_write_data
}

40
lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
class Control extends Module {
val io = IO(new Bundle {
val jump_flag = Input(Bool())
val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val memory_read_enable_ex = Input(Bool())
val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val if_flush = Output(Bool())
val id_flush = Output(Bool())
val pc_stall = Output(Bool())
val if_stall = Output(Bool())
})
// Lab3(Forward)
io.if_flush := false.B
io.id_flush := false.B
io.pc_stall := false.B
io.if_stall := false.B
// Lab3(Forward) End
}

108
lab3/src/main/scala/riscv/core/fivestage_forward/EX2MEM.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class EX2MEM extends Module {
val io = IO(new Bundle() {
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val funct3 = Input(UInt(3.W))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val alu_result = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_funct3 = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.AddrBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val funct3 = Module(new PipelineRegister(3))
funct3.io.in := io.funct3
funct3.io.stall := stall
funct3.io.flush := flush
io.output_funct3 := funct3.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := flush
io.output_reg2_data := reg2_data.io.out
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_forward/Execute.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util._
import riscv.Parameters
import riscv.core.{ALU, ALUControl}
class Execute extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate_id = Input(UInt(Parameters.DataWidth))
val aluop1_source_id = Input(UInt(1.W))
val aluop2_source_id = Input(UInt(1.W))
val csr_read_data_id = Input(UInt(Parameters.DataWidth))
val forward_from_mem = Input(UInt(Parameters.DataWidth))
val forward_from_wb = Input(UInt(Parameters.DataWidth))
val reg1_forward = Input(UInt(2.W))
val reg2_forward = Input(UInt(2.W))
val interrupt_assert_clint = Input(Bool())
val interrupt_handler_address_clint = Input(UInt(Parameters.AddrWidth))
val mem_alu_result = Output(UInt(Parameters.DataWidth))
val mem_reg2_data = Output(UInt(Parameters.DataWidth))
val csr_write_data = Output(UInt(Parameters.DataWidth))
val if_jump_flag = Output(Bool())
val if_jump_address = Output(UInt(Parameters.AddrWidth))
val clint_jump_flag = Output(Bool())
val clint_jump_address = Output(UInt(Parameters.AddrWidth))
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val uimm = io.instruction(19, 15)
// ALU compute
val alu = Module(new ALU)
val alu_ctrl = Module(new ALUControl)
alu_ctrl.io.opcode := opcode
alu_ctrl.io.funct3 := funct3
alu_ctrl.io.funct7 := funct7
alu.io.func := alu_ctrl.io.alu_funct
// Lab3(Forward)
val reg1_data = 0.U
val reg2_data = 0.U
// Lab3(Forward) End
alu.io.op1 := Mux(
io.aluop1_source_id === ALUOp1Source.InstructionAddress,
io.instruction_address,
reg1_data
)
alu.io.op2 := Mux(
io.aluop2_source_id === ALUOp2Source.Immediate,
io.immediate_id,
reg2_data
)
io.mem_alu_result := alu.io.result
io.mem_reg2_data := reg2_data
io.csr_write_data := MuxLookup(funct3, 0.U, IndexedSeq(
InstructionsTypeCSR.csrrw -> reg1_data,
InstructionsTypeCSR.csrrc -> io.csr_read_data_id.&((~reg1_data).asUInt),
InstructionsTypeCSR.csrrs -> io.csr_read_data_id.|(reg1_data),
InstructionsTypeCSR.csrrwi -> Cat(0.U(27.W), uimm),
InstructionsTypeCSR.csrrci -> io.csr_read_data_id.&((~Cat(0.U(27.W), uimm)).asUInt),
InstructionsTypeCSR.csrrsi -> io.csr_read_data_id.|(Cat(0.U(27.W), uimm)),
))
// jump and interrupt
val instruction_jump_flag = (opcode === Instructions.jal) ||
(opcode === Instructions.jalr) ||
(opcode === InstructionTypes.B) && MuxLookup(
funct3,
false.B,
IndexedSeq(
InstructionsTypeB.beq -> (reg1_data === reg2_data),
InstructionsTypeB.bne -> (reg1_data =/= reg2_data),
InstructionsTypeB.blt -> (reg1_data.asSInt < reg2_data.asSInt),
InstructionsTypeB.bge -> (reg1_data.asSInt >= reg2_data.asSInt),
InstructionsTypeB.bltu -> (reg1_data.asUInt < reg2_data.asUInt),
InstructionsTypeB.bgeu -> (reg1_data.asUInt >= reg2_data.asUInt)
)
)
io.clint_jump_flag := instruction_jump_flag
io.clint_jump_address := alu.io.result
io.if_jump_flag := io.interrupt_assert_clint || instruction_jump_flag
io.if_jump_address := Mux(io.interrupt_assert_clint,
io.interrupt_handler_address_clint,
alu.io.result
)
}

44
lab3/src/main/scala/riscv/core/fivestage_forward/Forwarding.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
object ForwardingType {
val NoForward = 0.U(2.W)
val ForwardFromMEM = 1.U(2.W)
val ForwardFromWB = 2.U(2.W)
}
class Forwarding extends Module {
val io = IO(new Bundle() {
val rs1_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_mem = Input(Bool())
val rd_wb = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_wb = Input(Bool())
// Forwarding Type
val reg1_forward_ex = Output(UInt(2.W))
val reg2_forward_ex = Output(UInt(2.W))
})
// Lab3(Forward)
io.reg1_forward_ex := 0.U
io.reg2_forward_ex := 0.U
// Lab3(Forward) End
}

164
lab3/src/main/scala/riscv/core/fivestage_forward/ID2EX.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class ID2EX extends Module {
val io = IO(new Bundle {
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val regs_reg1_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_enable = Input(Bool())
val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_source = Input(UInt(2.W))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate = Input(UInt(Parameters.DataWidth))
val aluop1_source = Input(UInt(1.W))
val aluop2_source = Input(UInt(1.W))
val csr_write_enable = Input(Bool())
val csr_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_source = Output(UInt(2.W))
val output_reg1_data = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_immediate = Output(UInt(Parameters.DataWidth))
val output_aluop1_source = Output(UInt(1.W))
val output_aluop2_source = Output(UInt(1.W))
val output_csr_write_enable = Output(Bool())
val output_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val regs_reg1_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg1_read_address.io.in := io.regs_reg1_read_address
regs_reg1_read_address.io.stall := stall
regs_reg1_read_address.io.flush := io.flush
io.output_regs_reg1_read_address := regs_reg1_read_address.io.out
val regs_reg2_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg2_read_address.io.in := io.regs_reg2_read_address
regs_reg2_read_address.io.stall := stall
regs_reg2_read_address.io.flush := io.flush
io.output_regs_reg2_read_address := regs_reg2_read_address.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := io.flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := io.flush
io.output_regs_write_address := regs_write_address.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := io.flush
io.output_regs_write_source := regs_write_source.io.out
val reg1_data = Module(new PipelineRegister())
reg1_data.io.in := io.reg1_data
reg1_data.io.stall := stall
reg1_data.io.flush := io.flush
io.output_reg1_data := reg1_data.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := io.flush
io.output_reg2_data := reg2_data.io.out
val immediate = Module(new PipelineRegister())
immediate.io.in := io.immediate
immediate.io.stall := stall
immediate.io.flush := io.flush
io.output_immediate := immediate.io.out
val aluop1_source = Module(new PipelineRegister(1))
aluop1_source.io.in := io.aluop1_source
aluop1_source.io.stall := stall
aluop1_source.io.flush := io.flush
io.output_aluop1_source := aluop1_source.io.out
val aluop2_source = Module(new PipelineRegister(1))
aluop2_source.io.in := io.aluop2_source
aluop2_source.io.stall := stall
aluop2_source.io.flush := io.flush
io.output_aluop2_source := aluop2_source.io.out
val csr_write_enable = Module(new PipelineRegister(1))
csr_write_enable.io.in := io.csr_write_enable
csr_write_enable.io.stall := stall
csr_write_enable.io.flush := io.flush
io.output_csr_write_enable := csr_write_enable.io.out
val csr_address = Module(new PipelineRegister(Parameters.CSRRegisterAddrBits))
csr_address.io.in := io.csr_address
csr_address.io.stall := stall
csr_address.io.flush := io.flush
io.output_csr_address := csr_address.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := io.flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := io.flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := io.flush
io.output_csr_read_data := csr_read_data.io.out
}

51
lab3/src/main/scala/riscv/core/fivestage_forward/IF2ID.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class IF2ID extends Module {
val io = IO(new Bundle {
val stall = Input(Bool())
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth))
})
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := io.stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := io.stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val interrupt_flag = Module(new PipelineRegister(Parameters.InterruptFlagBits))
interrupt_flag.io.in := io.interrupt_flag
interrupt_flag.io.stall := io.stall
interrupt_flag.io.flush := io.flush
io.output_interrupt_flag := interrupt_flag.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_forward/InstructionDecode.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util._
import riscv.Parameters
object InstructionTypes {
val L = "b0000011".U
val I = "b0010011".U
val S = "b0100011".U
val RM = "b0110011".U
val B = "b1100011".U
}
object Instructions {
val lui = "b0110111".U
val nop = "b0000001".U
val jal = "b1101111".U
val jalr = "b1100111".U
val auipc = "b0010111".U
val csr = "b1110011".U
val fence = "b0001111".U
}
object InstructionsTypeL {
val lb = "b000".U
val lh = "b001".U
val lw = "b010".U
val lbu = "b100".U
val lhu = "b101".U
}
object InstructionsTypeI {
val addi = 0.U
val slli = 1.U
val slti = 2.U
val sltiu = 3.U
val xori = 4.U
val sri = 5.U
val ori = 6.U
val andi = 7.U
}
object InstructionsTypeS {
val sb = "b000".U
val sh = "b001".U
val sw = "b010".U
}
object InstructionsTypeR {
val add_sub = 0.U
val sll = 1.U
val slt = 2.U
val sltu = 3.U
val xor = 4.U
val sr = 5.U
val or = 6.U
val and = 7.U
}
object InstructionsTypeM {
val mul = 0.U
val mulh = 1.U
val mulhsu = 2.U
val mulhum = 3.U
val div = 4.U
val divu = 5.U
val rem = 6.U
val remu = 7.U
}
object InstructionsTypeB {
val beq = "b000".U
val bne = "b001".U
val blt = "b100".U
val bge = "b101".U
val bltu = "b110".U
val bgeu = "b111".U
}
object InstructionsTypeCSR {
val csrrw = "b001".U
val csrrs = "b010".U
val csrrc = "b011".U
val csrrwi = "b101".U
val csrrsi = "b110".U
val csrrci = "b111".U
}
object InstructionsNop {
val nop = 0x00000013L.U(Parameters.DataWidth)
}
object InstructionsRet {
val mret = 0x30200073L.U(Parameters.DataWidth)
val ret = 0x00008067L.U(Parameters.DataWidth)
}
object InstructionsEnv {
val ecall = 0x00000073L.U(Parameters.DataWidth)
val ebreak = 0x00100073L.U(Parameters.DataWidth)
}
object ALUOp1Source {
val Register = 0.U(1.W)
val InstructionAddress = 1.U(1.W)
}
object ALUOp2Source {
val Register = 0.U(1.W)
val Immediate = 1.U(1.W)
}
object RegWriteSource {
val ALUResult = 0.U(2.W)
val Memory = 1.U(2.W)
val CSR = 2.U(2.W)
val NextInstructionAddress = 3.U(2.W)
}
class InstructionDecode extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_immediate = Output(UInt(Parameters.DataWidth))
val ex_aluop1_source = Output(Bool())
val ex_aluop2_source = Output(Bool())
val ex_memory_read_enable = Output(Bool())
val ex_memory_write_enable = Output(Bool())
val ex_reg_write_source = Output(UInt(2.W))
val ex_reg_write_enable = Output(Bool())
val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val ex_csr_write_enable = Output(Bool())
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val rd = io.instruction(11, 7)
val rs1 = io.instruction(19, 15)
val rs2 = io.instruction(24, 20)
io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
io.regs_reg2_read_address := rs2
io.ex_immediate := MuxLookup(
opcode,
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
IndexedSeq(
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
)
)
io.ex_aluop1_source := Mux(
opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
ALUOp1Source.InstructionAddress,
ALUOp1Source.Register
)
io.ex_aluop2_source := Mux(
opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
io.ex_memory_read_enable := opcode === InstructionTypes.L
io.ex_memory_write_enable := opcode === InstructionTypes.S
io.ex_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult,
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.csr -> RegWriteSource.CSR,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)
io.ex_reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
(opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr)
io.ex_reg_write_address := io.instruction(11, 7)
io.ex_csr_address := io.instruction(31, 20)
io.ex_csr_write_enable := (opcode === Instructions.csr) && (
funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi ||
funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi ||
funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci
)
}

48
lab3/src/main/scala/riscv/core/fivestage_forward/InstructionFetch.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util.MuxCase
import riscv.Parameters
object ProgramCounter {
val EntryAddress = Parameters.EntryAddress
}
class InstructionFetch extends Module {
val io = IO(new Bundle {
val stall_flag_ctrl = Input(Bool())
val jump_flag_id = Input(Bool())
val jump_address_id = Input(UInt(Parameters.AddrWidth))
val rom_instruction = Input(UInt(Parameters.DataWidth))
val instruction_valid = Input(Bool())
val instruction_address = Output(UInt(Parameters.AddrWidth))
val id_instruction = Output(UInt(Parameters.InstructionWidth))
})
val pc = RegInit(ProgramCounter.EntryAddress)
pc := MuxCase(
pc + 4.U,
IndexedSeq(
(io.jump_flag_id && !io.stall_flag_ctrl) -> io.jump_address_id,
(io.stall_flag_ctrl || !io.instruction_valid) -> pc
)
)
io.instruction_address := pc
io.id_instruction := Mux(io.instruction_valid, io.rom_instruction, InstructionsNop.nop)
}

83
lab3/src/main/scala/riscv/core/fivestage_forward/MEM2WB.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class MEM2WB extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_memory_read_data = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_data = Module(new PipelineRegister())
memory_read_data.io.in := io.memory_read_data
memory_read_data.io.stall := stall
memory_read_data.io.flush := flush
io.output_memory_read_data := memory_read_data.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.InstructionBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

109
lab3/src/main/scala/riscv/core/fivestage_forward/MemoryAccess.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util._
import peripheral.RAMBundle
import riscv.Parameters
class MemoryAccess extends Module {
val io = IO(new Bundle() {
val alu_result = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val funct3 = Input(UInt(3.W))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
val forward_data = Output(UInt(Parameters.DataWidth))
val bundle = Flipped(new RAMBundle)
})
val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
io.bundle.write_enable := io.memory_write_enable
io.bundle.write_data := 0.U
io.bundle.address := io.alu_result
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
io.wb_memory_read_data := 0.U
when(io.memory_read_enable) {
val data = io.bundle.read_data
io.wb_memory_read_data := MuxLookup(
io.funct3,
0.U,
IndexedSeq(
InstructionsTypeL.lb -> MuxLookup(
mem_address_index,
Cat(Fill(24, data(31)), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
2.U -> Cat(Fill(24, data(23)), data(23, 16))
)
),
InstructionsTypeL.lbu -> MuxLookup(
mem_address_index,
Cat(Fill(24, 0.U), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
2.U -> Cat(Fill(24, 0.U), data(23, 16))
)
),
InstructionsTypeL.lh -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, data(15)), data(15, 0)),
Cat(Fill(16, data(31)), data(31, 16))
),
InstructionsTypeL.lhu -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, 0.U), data(15, 0)),
Cat(Fill(16, 0.U), data(31, 16))
),
InstructionsTypeL.lw -> data
)
)
}.elsewhen(io.memory_write_enable) {
io.bundle.write_data := io.reg2_data
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
when(io.funct3 === InstructionsTypeS.sb) {
io.bundle.write_strobe(mem_address_index) := true.B
io.bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
}.elsewhen(io.funct3 === InstructionsTypeS.sh) {
when(mem_address_index === 0.U) {
for (i <- 0 until Parameters.WordSize / 2) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
}.otherwise {
for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
.WordSize / 2 * Parameters.ByteBits)
}
}.elsewhen(io.funct3 === InstructionsTypeS.sw) {
for (i <- 0 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
}
}
io.forward_data := Mux(io.regs_write_source === RegWriteSource.CSR, io.csr_read_data, io.alu_result)
}

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lab3/src/main/scala/riscv/core/fivestage_forward/WriteBack.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_forward
import chisel3._
import chisel3.util._
import riscv.Parameters
class WriteBack extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_data = Output(UInt(Parameters.DataWidth))
})
io.regs_write_data := MuxLookup(
io.regs_write_source,
io.alu_result,
IndexedSeq(
RegWriteSource.Memory -> io.memory_read_data,
RegWriteSource.CSR -> io.csr_read_data,
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
)
)
}

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lab3/src/main/scala/riscv/core/fivestage_stall/CLINT.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util.MuxLookup
import riscv.Parameters
object InterruptStatus {
val None = 0x0.U(8.W)
val Timer0 = 0x1.U(8.W)
val Ret = 0xFF.U(8.W)
}
class CSRDirectAccessBundle extends Bundle {
val mstatus = Input(UInt(Parameters.DataWidth))
val mepc = Input(UInt(Parameters.DataWidth))
val mcause = Input(UInt(Parameters.DataWidth))
val mtvec = Input(UInt(Parameters.DataWidth))
val mstatus_write_data = Output(UInt(Parameters.DataWidth))
val mepc_write_data = Output(UInt(Parameters.DataWidth))
val mcause_write_data = Output(UInt(Parameters.DataWidth))
val direct_write_enable = Output(Bool())
}
// Core Local Interrupt Controller
class CLINT extends Module {
val io = IO(new Bundle {
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val instruction_ex = Input(UInt(Parameters.InstructionWidth))
val instruction_address_if = Input(UInt(Parameters.AddrWidth))
val instruction_address_id = Input(UInt(Parameters.AddrWidth))
val jump_flag = Input(Bool())
val jump_address = Input(UInt(Parameters.AddrWidth))
val ex_interrupt_handler_address = Output(UInt(Parameters.AddrWidth))
val ex_interrupt_assert = Output(Bool())
val csr_bundle = new CSRDirectAccessBundle
})
val interrupt_enable = io.csr_bundle.mstatus(3)
val jumpping = RegNext(io.jump_flag || io.ex_interrupt_assert)
val instruction_address = Mux(
io.jump_flag,
io.jump_address,
Mux(jumpping, io.instruction_address_if, io.instruction_address_id)
)
val mstatus_disable_interrupt = io.csr_bundle.mstatus(31, 4) ## 0.U(1.W) ## io.csr_bundle.mstatus(2, 0)
val mstatus_recover_interrupt = io.csr_bundle.mstatus(31, 4) ## io.csr_bundle.mstatus(7) ## io.csr_bundle.mstatus(2, 0)
when(io.instruction_ex === InstructionsEnv.ecall || io.instruction_ex === InstructionsEnv.ebreak) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := MuxLookup(
io.instruction_ex,
10.U,
IndexedSeq(
InstructionsEnv.ecall -> 11.U,
InstructionsEnv.ebreak -> 3.U,
)
)
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.interrupt_flag =/= InterruptStatus.None && interrupt_enable) {
io.csr_bundle.mstatus_write_data := mstatus_disable_interrupt
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := Mux(io.interrupt_flag(0), 0x80000007L.U, 0x8000000BL.U)
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mtvec
}.elsewhen(io.instruction_ex === InstructionsRet.mret) {
io.csr_bundle.mstatus_write_data := mstatus_recover_interrupt
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := true.B
io.ex_interrupt_assert := true.B
io.ex_interrupt_handler_address := io.csr_bundle.mepc
}.otherwise {
io.csr_bundle.mstatus_write_data := io.csr_bundle.mstatus
io.csr_bundle.mepc_write_data := io.csr_bundle.mepc
io.csr_bundle.mcause_write_data := io.csr_bundle.mcause
io.csr_bundle.direct_write_enable := false.B
io.ex_interrupt_assert := false.B
io.ex_interrupt_handler_address := 0.U
}
}

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lab3/src/main/scala/riscv/core/fivestage_stall/CPU.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
import riscv.core.{CPUBundle, CSR, RegisterFile}
class CPU extends Module {
val io = IO(new CPUBundle)
val ctrl = Module(new Control)
val regs = Module(new RegisterFile)
val inst_fetch = Module(new InstructionFetch)
val if2id = Module(new IF2ID)
val id = Module(new InstructionDecode)
val id2ex = Module(new ID2EX)
val ex = Module(new Execute)
val ex2mem = Module(new EX2MEM)
val mem = Module(new MemoryAccess)
val mem2wb = Module(new MEM2WB)
val wb = Module(new WriteBack)
val clint = Module(new CLINT)
val csr_regs = Module(new CSR)
ctrl.io.jump_flag := ex.io.if_jump_flag
ctrl.io.rs1_id := id.io.regs_reg1_read_address
ctrl.io.rs2_id := id.io.regs_reg2_read_address
ctrl.io.rd_ex := id2ex.io.output_regs_write_address
ctrl.io.reg_write_enable_ex := id2ex.io.output_regs_write_enable
ctrl.io.rd_mem := ex2mem.io.output_regs_write_address
ctrl.io.reg_write_enable_mem := ex2mem.io.output_regs_write_enable
regs.io.write_enable := mem2wb.io.output_regs_write_enable
regs.io.write_address := mem2wb.io.output_regs_write_address
regs.io.write_data := wb.io.regs_write_data
regs.io.read_address1 := id.io.regs_reg1_read_address
regs.io.read_address2 := id.io.regs_reg2_read_address
regs.io.debug_read_address := io.debug_read_address
io.debug_read_data := regs.io.debug_read_data
io.instruction_address := inst_fetch.io.instruction_address
inst_fetch.io.stall_flag_ctrl := ctrl.io.pc_stall
inst_fetch.io.jump_flag_id := ex.io.if_jump_flag
inst_fetch.io.jump_address_id := ex.io.if_jump_address
inst_fetch.io.rom_instruction := io.instruction
inst_fetch.io.instruction_valid := io.instruction_valid
if2id.io.stall := ctrl.io.if_stall
if2id.io.flush := ctrl.io.if_flush
if2id.io.instruction := inst_fetch.io.id_instruction
if2id.io.instruction_address := inst_fetch.io.instruction_address
if2id.io.interrupt_flag := io.interrupt_flag
id.io.instruction := if2id.io.output_instruction
id2ex.io.flush := ctrl.io.id_flush
id2ex.io.instruction := if2id.io.output_instruction
id2ex.io.instruction_address := if2id.io.output_instruction_address
id2ex.io.reg1_data := regs.io.read_data1
id2ex.io.reg2_data := regs.io.read_data2
id2ex.io.regs_reg1_read_address := id.io.regs_reg1_read_address
id2ex.io.regs_reg2_read_address := id.io.regs_reg2_read_address
id2ex.io.regs_write_enable := id.io.ex_reg_write_enable
id2ex.io.regs_write_address := id.io.ex_reg_write_address
id2ex.io.regs_write_source := id.io.ex_reg_write_source
id2ex.io.immediate := id.io.ex_immediate
id2ex.io.aluop1_source := id.io.ex_aluop1_source
id2ex.io.aluop2_source := id.io.ex_aluop2_source
id2ex.io.csr_write_enable := id.io.ex_csr_write_enable
id2ex.io.csr_address := id.io.ex_csr_address
id2ex.io.memory_read_enable := id.io.ex_memory_read_enable
id2ex.io.memory_write_enable := id.io.ex_memory_write_enable
id2ex.io.csr_read_data := csr_regs.io.id_reg_read_data
ex.io.instruction := id2ex.io.output_instruction
ex.io.instruction_address := id2ex.io.output_instruction_address
ex.io.reg1_data := id2ex.io.output_reg1_data
ex.io.reg2_data := id2ex.io.output_reg2_data
ex.io.immediate_id := id2ex.io.output_immediate
ex.io.aluop1_source_id := id2ex.io.output_aluop1_source
ex.io.aluop2_source_id := id2ex.io.output_aluop2_source
ex.io.csr_read_data_id := id2ex.io.output_csr_read_data
ex.io.interrupt_assert_clint := clint.io.ex_interrupt_assert
ex.io.interrupt_handler_address_clint := clint.io.ex_interrupt_handler_address
ex2mem.io.regs_write_enable := id2ex.io.output_regs_write_enable
ex2mem.io.regs_write_source := id2ex.io.output_regs_write_source
ex2mem.io.regs_write_address := id2ex.io.output_regs_write_address
ex2mem.io.instruction_address := id2ex.io.output_instruction_address
ex2mem.io.funct3 := id2ex.io.output_instruction(14, 12)
ex2mem.io.reg2_data := ex.io.mem_reg2_data
ex2mem.io.memory_read_enable := id2ex.io.output_memory_read_enable
ex2mem.io.memory_write_enable := id2ex.io.output_memory_write_enable
ex2mem.io.alu_result := ex.io.mem_alu_result
ex2mem.io.csr_read_data := id2ex.io.output_csr_read_data
mem.io.alu_result := ex2mem.io.output_alu_result
mem.io.reg2_data := ex2mem.io.output_reg2_data
mem.io.memory_read_enable := ex2mem.io.output_memory_read_enable
mem.io.memory_write_enable := ex2mem.io.output_memory_write_enable
mem.io.funct3 := ex2mem.io.output_funct3
mem.io.regs_write_source := ex2mem.io.output_regs_write_source
mem.io.csr_read_data := ex2mem.io.output_csr_read_data
io.device_select := mem.io.bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
io.memory_bundle <> mem.io.bundle
io.memory_bundle.address := 0.U(Parameters.SlaveDeviceCountBits.W) ## mem.io.bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0)
mem2wb.io.instruction_address := ex2mem.io.output_instruction_address
mem2wb.io.alu_result := ex2mem.io.output_alu_result
mem2wb.io.regs_write_enable := ex2mem.io.output_regs_write_enable
mem2wb.io.regs_write_source := ex2mem.io.output_regs_write_source
mem2wb.io.regs_write_address := ex2mem.io.output_regs_write_address
mem2wb.io.memory_read_data := mem.io.wb_memory_read_data
mem2wb.io.csr_read_data := ex2mem.io.output_csr_read_data
wb.io.instruction_address := mem2wb.io.output_instruction_address
wb.io.alu_result := mem2wb.io.output_alu_result
wb.io.memory_read_data := mem2wb.io.output_memory_read_data
wb.io.regs_write_source := mem2wb.io.output_regs_write_source
wb.io.csr_read_data := mem2wb.io.output_csr_read_data
clint.io.instruction_address_if := inst_fetch.io.instruction_address
clint.io.instruction_address_id := if2id.io.output_instruction_address
clint.io.instruction_ex := id2ex.io.output_instruction
clint.io.jump_flag := ex.io.clint_jump_flag
clint.io.jump_address := ex.io.clint_jump_address
clint.io.interrupt_flag := if2id.io.output_interrupt_flag
clint.io.csr_bundle <> csr_regs.io.clint_access_bundle
csr_regs.io.reg_read_address_id := id.io.ex_csr_address
csr_regs.io.reg_write_enable_ex := id2ex.io.output_csr_write_enable
csr_regs.io.reg_write_address_ex := id2ex.io.output_csr_address
csr_regs.io.reg_write_data_ex := ex.io.csr_write_data
}

43
lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
class Control extends Module {
val io = IO(new Bundle {
val jump_flag = Input(Bool())
val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_ex = Input(Bool())
val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val reg_write_enable_mem = Input(Bool())
val if_flush = Output(Bool())
val id_flush = Output(Bool())
val pc_stall = Output(Bool())
val if_stall = Output(Bool())
})
// Lab3(Stall)
io.if_flush := false.B
io.id_flush := false.B
io.pc_stall := false.B
io.if_stall := false.B
// Lab3(Stall) End
}

108
lab3/src/main/scala/riscv/core/fivestage_stall/EX2MEM.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class EX2MEM extends Module {
val io = IO(new Bundle() {
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val funct3 = Input(UInt(3.W))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val alu_result = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_funct3 = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.AddrBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val funct3 = Module(new PipelineRegister(3))
funct3.io.in := io.funct3
funct3.io.stall := stall
funct3.io.flush := flush
io.output_funct3 := funct3.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := flush
io.output_reg2_data := reg2_data.io.out
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

101
lab3/src/main/scala/riscv/core/fivestage_stall/Execute.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util._
import riscv.Parameters
import riscv.core.{ALU, ALUControl}
class Execute extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate_id = Input(UInt(Parameters.DataWidth))
val aluop1_source_id = Input(UInt(1.W))
val aluop2_source_id = Input(UInt(1.W))
val csr_read_data_id = Input(UInt(Parameters.DataWidth))
val interrupt_assert_clint = Input(Bool())
val interrupt_handler_address_clint = Input(UInt(Parameters.AddrWidth))
val mem_alu_result = Output(UInt(Parameters.DataWidth))
val mem_reg2_data = Output(UInt(Parameters.DataWidth))
val csr_write_data = Output(UInt(Parameters.DataWidth))
val if_jump_flag = Output(Bool())
val if_jump_address = Output(UInt(Parameters.AddrWidth))
val clint_jump_flag = Output(Bool())
val clint_jump_address = Output(UInt(Parameters.AddrWidth))
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val uimm = io.instruction(19, 15)
// ALU compute
val alu = Module(new ALU)
val alu_ctrl = Module(new ALUControl)
alu_ctrl.io.opcode := opcode
alu_ctrl.io.funct3 := funct3
alu_ctrl.io.funct7 := funct7
alu.io.func := alu_ctrl.io.alu_funct
alu.io.op1 := Mux(
io.aluop1_source_id === ALUOp1Source.InstructionAddress,
io.instruction_address,
io.reg1_data
)
alu.io.op2 := Mux(
io.aluop2_source_id === ALUOp2Source.Immediate,
io.immediate_id,
io.reg2_data
)
io.mem_alu_result := alu.io.result
io.mem_reg2_data := io.reg2_data
io.csr_write_data := MuxLookup(funct3, 0.U, IndexedSeq(
InstructionsTypeCSR.csrrw -> io.reg1_data,
InstructionsTypeCSR.csrrc -> io.csr_read_data_id.&((~io.reg1_data).asUInt),
InstructionsTypeCSR.csrrs -> io.csr_read_data_id.|(io.reg1_data),
InstructionsTypeCSR.csrrwi -> Cat(0.U(27.W), uimm),
InstructionsTypeCSR.csrrci -> io.csr_read_data_id.&((~Cat(0.U(27.W), uimm)).asUInt),
InstructionsTypeCSR.csrrsi -> io.csr_read_data_id.|(Cat(0.U(27.W), uimm)),
))
// jump and interrupt
val instruction_jump_flag = (opcode === Instructions.jal) ||
(opcode === Instructions.jalr) ||
(opcode === InstructionTypes.B) && MuxLookup(
funct3,
false.B,
IndexedSeq(
InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
InstructionsTypeB.blt -> (io.reg1_data.asSInt < io.reg2_data.asSInt),
InstructionsTypeB.bge -> (io.reg1_data.asSInt >= io.reg2_data.asSInt),
InstructionsTypeB.bltu -> (io.reg1_data.asUInt < io.reg2_data.asUInt),
InstructionsTypeB.bgeu -> (io.reg1_data.asUInt >= io.reg2_data.asUInt)
)
)
io.clint_jump_flag := instruction_jump_flag
io.clint_jump_address := alu.io.result
io.if_jump_flag := io.interrupt_assert_clint || instruction_jump_flag
io.if_jump_address := Mux(io.interrupt_assert_clint,
io.interrupt_handler_address_clint,
alu.io.result
)
}

164
lab3/src/main/scala/riscv/core/fivestage_stall/ID2EX.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class ID2EX extends Module {
val io = IO(new Bundle {
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val regs_reg1_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_enable = Input(Bool())
val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_source = Input(UInt(2.W))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate = Input(UInt(Parameters.DataWidth))
val aluop1_source = Input(UInt(1.W))
val aluop2_source = Input(UInt(1.W))
val csr_write_enable = Input(Bool())
val csr_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_source = Output(UInt(2.W))
val output_reg1_data = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_immediate = Output(UInt(Parameters.DataWidth))
val output_aluop1_source = Output(UInt(1.W))
val output_aluop2_source = Output(UInt(1.W))
val output_csr_write_enable = Output(Bool())
val output_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val regs_reg1_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg1_read_address.io.in := io.regs_reg1_read_address
regs_reg1_read_address.io.stall := stall
regs_reg1_read_address.io.flush := io.flush
io.output_regs_reg1_read_address := regs_reg1_read_address.io.out
val regs_reg2_read_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_reg2_read_address.io.in := io.regs_reg2_read_address
regs_reg2_read_address.io.stall := stall
regs_reg2_read_address.io.flush := io.flush
io.output_regs_reg2_read_address := regs_reg2_read_address.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := io.flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := io.flush
io.output_regs_write_address := regs_write_address.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := io.flush
io.output_regs_write_source := regs_write_source.io.out
val reg1_data = Module(new PipelineRegister())
reg1_data.io.in := io.reg1_data
reg1_data.io.stall := stall
reg1_data.io.flush := io.flush
io.output_reg1_data := reg1_data.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := io.flush
io.output_reg2_data := reg2_data.io.out
val immediate = Module(new PipelineRegister())
immediate.io.in := io.immediate
immediate.io.stall := stall
immediate.io.flush := io.flush
io.output_immediate := immediate.io.out
val aluop1_source = Module(new PipelineRegister(1))
aluop1_source.io.in := io.aluop1_source
aluop1_source.io.stall := stall
aluop1_source.io.flush := io.flush
io.output_aluop1_source := aluop1_source.io.out
val aluop2_source = Module(new PipelineRegister(1))
aluop2_source.io.in := io.aluop2_source
aluop2_source.io.stall := stall
aluop2_source.io.flush := io.flush
io.output_aluop2_source := aluop2_source.io.out
val csr_write_enable = Module(new PipelineRegister(1))
csr_write_enable.io.in := io.csr_write_enable
csr_write_enable.io.stall := stall
csr_write_enable.io.flush := io.flush
io.output_csr_write_enable := csr_write_enable.io.out
val csr_address = Module(new PipelineRegister(Parameters.CSRRegisterAddrBits))
csr_address.io.in := io.csr_address
csr_address.io.stall := stall
csr_address.io.flush := io.flush
io.output_csr_address := csr_address.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := io.flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := io.flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := io.flush
io.output_csr_read_data := csr_read_data.io.out
}

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lab3/src/main/scala/riscv/core/fivestage_stall/IF2ID.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class IF2ID extends Module {
val io = IO(new Bundle {
val stall = Input(Bool())
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth))
})
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := io.stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := io.stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val interrupt_flag = Module(new PipelineRegister(Parameters.InterruptFlagBits))
interrupt_flag.io.in := io.interrupt_flag
interrupt_flag.io.stall := io.stall
interrupt_flag.io.flush := io.flush
io.output_interrupt_flag := interrupt_flag.io.out
}

207
lab3/src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util._
import riscv.Parameters
object InstructionTypes {
val L = "b0000011".U
val I = "b0010011".U
val S = "b0100011".U
val RM = "b0110011".U
val B = "b1100011".U
}
object Instructions {
val lui = "b0110111".U
val nop = "b0000001".U
val jal = "b1101111".U
val jalr = "b1100111".U
val auipc = "b0010111".U
val csr = "b1110011".U
val fence = "b0001111".U
}
object InstructionsTypeL {
val lb = "b000".U
val lh = "b001".U
val lw = "b010".U
val lbu = "b100".U
val lhu = "b101".U
}
object InstructionsTypeI {
val addi = 0.U
val slli = 1.U
val slti = 2.U
val sltiu = 3.U
val xori = 4.U
val sri = 5.U
val ori = 6.U
val andi = 7.U
}
object InstructionsTypeS {
val sb = "b000".U
val sh = "b001".U
val sw = "b010".U
}
object InstructionsTypeR {
val add_sub = 0.U
val sll = 1.U
val slt = 2.U
val sltu = 3.U
val xor = 4.U
val sr = 5.U
val or = 6.U
val and = 7.U
}
object InstructionsTypeM {
val mul = 0.U
val mulh = 1.U
val mulhsu = 2.U
val mulhum = 3.U
val div = 4.U
val divu = 5.U
val rem = 6.U
val remu = 7.U
}
object InstructionsTypeB {
val beq = "b000".U
val bne = "b001".U
val blt = "b100".U
val bge = "b101".U
val bltu = "b110".U
val bgeu = "b111".U
}
object InstructionsTypeCSR {
val csrrw = "b001".U
val csrrs = "b010".U
val csrrc = "b011".U
val csrrwi = "b101".U
val csrrsi = "b110".U
val csrrci = "b111".U
}
object InstructionsNop {
val nop = 0x00000013L.U(Parameters.DataWidth)
}
object InstructionsRet {
val mret = 0x30200073L.U(Parameters.DataWidth)
val ret = 0x00008067L.U(Parameters.DataWidth)
}
object InstructionsEnv {
val ecall = 0x00000073L.U(Parameters.DataWidth)
val ebreak = 0x00100073L.U(Parameters.DataWidth)
}
object ALUOp1Source {
val Register = 0.U(1.W)
val InstructionAddress = 1.U(1.W)
}
object ALUOp2Source {
val Register = 0.U(1.W)
val Immediate = 1.U(1.W)
}
object RegWriteSource {
val ALUResult = 0.U(2.W)
val Memory = 1.U(2.W)
val CSR = 2.U(2.W)
val NextInstructionAddress = 3.U(2.W)
}
class InstructionDecode extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_immediate = Output(UInt(Parameters.DataWidth))
val ex_aluop1_source = Output(Bool())
val ex_aluop2_source = Output(Bool())
val ex_memory_read_enable = Output(Bool())
val ex_memory_write_enable = Output(Bool())
val ex_reg_write_source = Output(UInt(2.W))
val ex_reg_write_enable = Output(Bool())
val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val ex_csr_write_enable = Output(Bool())
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val rd = io.instruction(11, 7)
val rs1 = io.instruction(19, 15)
val rs2 = io.instruction(24, 20)
io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
io.regs_reg2_read_address := rs2
io.ex_immediate := MuxLookup(
opcode,
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
IndexedSeq(
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
)
)
io.ex_aluop1_source := Mux(
opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
ALUOp1Source.InstructionAddress,
ALUOp1Source.Register
)
io.ex_aluop2_source := Mux(
opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
io.ex_memory_read_enable := opcode === InstructionTypes.L
io.ex_memory_write_enable := opcode === InstructionTypes.S
io.ex_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult,
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.csr -> RegWriteSource.CSR,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)
io.ex_reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
(opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr)
io.ex_reg_write_address := io.instruction(11, 7)
io.ex_csr_address := io.instruction(31, 20)
io.ex_csr_write_enable := (opcode === Instructions.csr) && (
funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi ||
funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi ||
funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci
)
}

48
lab3/src/main/scala/riscv/core/fivestage_stall/InstructionFetch.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util.MuxCase
import riscv.Parameters
object ProgramCounter {
val EntryAddress = Parameters.EntryAddress
}
class InstructionFetch extends Module {
val io = IO(new Bundle {
val stall_flag_ctrl = Input(Bool())
val jump_flag_id = Input(Bool())
val jump_address_id = Input(UInt(Parameters.AddrWidth))
val rom_instruction = Input(UInt(Parameters.DataWidth))
val instruction_valid = Input(Bool())
val instruction_address = Output(UInt(Parameters.AddrWidth))
val id_instruction = Output(UInt(Parameters.InstructionWidth))
})
val pc = RegInit(ProgramCounter.EntryAddress)
pc := MuxCase(
pc + 4.U,
IndexedSeq(
(io.jump_flag_id && !io.stall_flag_ctrl) -> io.jump_address_id,
(io.stall_flag_ctrl || !io.instruction_valid) -> pc
)
)
io.instruction_address := pc
io.id_instruction := Mux(io.instruction_valid, io.rom_instruction, InstructionsNop.nop)
}

83
lab3/src/main/scala/riscv/core/fivestage_stall/MEM2WB.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class MEM2WB extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val regs_write_enable = Input(Bool())
val regs_write_source = Input(UInt(2.W))
val regs_write_address = Input(UInt(Parameters.AddrWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_alu_result = Output(UInt(Parameters.DataWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_source = Output(UInt(2.W))
val output_regs_write_address = Output(UInt(Parameters.AddrWidth))
val output_memory_read_data = Output(UInt(Parameters.DataWidth))
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val flush = false.B
val alu_result = Module(new PipelineRegister())
alu_result.io.in := io.alu_result
alu_result.io.stall := stall
alu_result.io.flush := flush
io.output_alu_result := alu_result.io.out
val memory_read_data = Module(new PipelineRegister())
memory_read_data.io.in := io.memory_read_data
memory_read_data.io.stall := stall
memory_read_data.io.flush := flush
io.output_memory_read_data := memory_read_data.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := flush
io.output_regs_write_source := regs_write_source.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := flush
io.output_regs_write_address := regs_write_address.io.out
val instruction_address = Module(new PipelineRegister(Parameters.InstructionBits))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := flush
io.output_instruction_address := instruction_address.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := flush
io.output_csr_read_data := csr_read_data.io.out
}

106
lab3/src/main/scala/riscv/core/fivestage_stall/MemoryAccess.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util._
import peripheral.RAMBundle
import riscv.Parameters
class MemoryAccess extends Module {
val io = IO(new Bundle() {
val alu_result = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val funct3 = Input(UInt(3.W))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
val bundle = Flipped(new RAMBundle)
})
val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
io.bundle.write_enable := io.memory_write_enable
io.bundle.write_data := 0.U
io.bundle.address := io.alu_result
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
io.wb_memory_read_data := 0.U
when(io.memory_read_enable) {
val data = io.bundle.read_data
io.wb_memory_read_data := MuxLookup(
io.funct3,
0.U,
IndexedSeq(
InstructionsTypeL.lb -> MuxLookup(
mem_address_index,
Cat(Fill(24, data(31)), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
2.U -> Cat(Fill(24, data(23)), data(23, 16))
)
),
InstructionsTypeL.lbu -> MuxLookup(
mem_address_index,
Cat(Fill(24, 0.U), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
2.U -> Cat(Fill(24, 0.U), data(23, 16))
)
),
InstructionsTypeL.lh -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, data(15)), data(15, 0)),
Cat(Fill(16, data(31)), data(31, 16))
),
InstructionsTypeL.lhu -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, 0.U), data(15, 0)),
Cat(Fill(16, 0.U), data(31, 16))
),
InstructionsTypeL.lw -> data
)
)
}.elsewhen(io.memory_write_enable) {
io.bundle.write_data := io.reg2_data
io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
when(io.funct3 === InstructionsTypeS.sb) {
io.bundle.write_strobe(mem_address_index) := true.B
io.bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
}.elsewhen(io.funct3 === InstructionsTypeS.sh) {
when(mem_address_index === 0.U) {
for (i <- 0 until Parameters.WordSize / 2) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
}.otherwise {
for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
io.bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
.WordSize / 2 * Parameters.ByteBits)
}
}.elsewhen(io.funct3 === InstructionsTypeS.sw) {
for (i <- 0 until Parameters.WordSize) {
io.bundle.write_strobe(i) := true.B
}
}
}
}

40
lab3/src/main/scala/riscv/core/fivestage_stall/WriteBack.scala Normal file
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// Copyright 2022 Canbin Huang
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.fivestage_stall
import chisel3._
import chisel3.util._
import riscv.Parameters
class WriteBack extends Module {
val io = IO(new Bundle() {
val instruction_address = Input(UInt(Parameters.AddrWidth))
val alu_result = Input(UInt(Parameters.DataWidth))
val memory_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_source = Input(UInt(2.W))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val regs_write_data = Output(UInt(Parameters.DataWidth))
})
io.regs_write_data := MuxLookup(
io.regs_write_source,
io.alu_result,
IndexedSeq(
RegWriteSource.Memory -> io.memory_read_data,
RegWriteSource.CSR -> io.csr_read_data,
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
)
)
}

88
lab3/src/main/scala/riscv/core/threestage/CLINT.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import chisel3.util.MuxLookup
import riscv.Parameters
object InterruptStatus {
val None = 0x0.U(8.W)
val Timer0 = 0x1.U(8.W)
val Ret = 0xFF.U(8.W)
}
class CSRDirectAccessBundle extends Bundle {
val mstatus = Input(UInt(Parameters.DataWidth))
val mepc = Input(UInt(Parameters.DataWidth))
val mcause = Input(UInt(Parameters.DataWidth))
val mtvec = Input(UInt(Parameters.DataWidth))
val mstatus_write_data = Output(UInt(Parameters.DataWidth))
val mepc_write_data = Output(UInt(Parameters.DataWidth))
val mcause_write_data = Output(UInt(Parameters.DataWidth))
val direct_write_enable = Output(Bool())
}
// Core Local Interrupt Controller
class CLINT extends Module {
val io = IO(new Bundle {
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val instruction_ex = Input(UInt(Parameters.InstructionWidth))
val instruction_address_if = Input(UInt(Parameters.AddrWidth))
val instruction_address_id = Input(UInt(Parameters.AddrWidth))
val jump_flag = Input(Bool())
val jump_address = Input(UInt(Parameters.AddrWidth))
val ex_interrupt_handler_address = Output(UInt(Parameters.AddrWidth))
val ex_interrupt_assert = Output(Bool())
val csr_bundle = new CSRDirectAccessBundle
})
val interrupt_enable = io.csr_bundle.mstatus(3)
val jumpping = RegNext(io.jump_flag || io.ex_interrupt_assert)
val instruction_address = Mux(
io.jump_flag,
io.jump_address,
Mux(jumpping, io.instruction_address_if, io.instruction_address_id)
)
val mstatus_disable_interrupt = io.csr_bundle.mstatus(31, 4) ## 0.U(1.W) ## io.csr_bundle.mstatus(2, 0)
val mstatus_recover_interrupt = io.csr_bundle.mstatus(31, 4) ## io.csr_bundle.mstatus(7) ## io.csr_bundle.mstatus(2, 0)
val exception = io.instruction_ex === InstructionsEnv.ecall || io.instruction_ex === InstructionsEnv.ebreak
val interrupt = io.interrupt_flag =/= InterruptStatus.None && interrupt_enable
val mret = io.instruction_ex === InstructionsRet.mret
val interrupt_assert = exception || interrupt || mret
io.csr_bundle.mstatus_write_data := Mux(mret, mstatus_recover_interrupt, mstatus_disable_interrupt)
io.csr_bundle.mepc_write_data := instruction_address
io.csr_bundle.mcause_write_data := Mux(
exception,
MuxLookup(
io.instruction_ex,
10.U,
IndexedSeq(
InstructionsEnv.ecall -> 11.U,
InstructionsEnv.ebreak -> 3.U,
)
),
Mux(io.interrupt_flag(0), 0x80000007L.U, 0x8000000BL.U)
)
io.csr_bundle.direct_write_enable := interrupt_assert
io.ex_interrupt_assert := interrupt_assert
io.ex_interrupt_handler_address := Mux(mret, io.csr_bundle.mepc, io.csr_bundle.mtvec)
}

104
lab3/src/main/scala/riscv/core/threestage/CPU.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import riscv.Parameters
import riscv.core.{CPUBundle, CSR, RegisterFile}
class CPU extends Module {
val io = IO(new CPUBundle)
val ctrl = Module(new Control)
val regs = Module(new RegisterFile)
val inst_fetch = Module(new InstructionFetch)
val if2id = Module(new IF2ID)
val id = Module(new InstructionDecode)
val id2ex = Module(new ID2EX)
val ex = Module(new Execute)
val clint = Module(new CLINT)
val csr_regs = Module(new CSR)
// Lab3(Flush)
if2id.io.flush := false.B
id2ex.io.flush := false.B
// Lab3(Flush) End
regs.io.write_enable := id2ex.io.output_regs_write_enable
regs.io.write_address := id2ex.io.output_regs_write_address
regs.io.write_data := ex.io.regs_write_data
regs.io.read_address1 := id.io.regs_reg1_read_address
regs.io.read_address2 := id.io.regs_reg2_read_address
regs.io.debug_read_address := io.debug_read_address
io.debug_read_data := regs.io.debug_read_data
io.instruction_address := inst_fetch.io.instruction_address
inst_fetch.io.jump_flag_ex := ex.io.if_jump_flag
inst_fetch.io.jump_address_ex := ex.io.if_jump_address
inst_fetch.io.rom_instruction := io.instruction
inst_fetch.io.instruction_valid := io.instruction_valid
if2id.io.instruction := inst_fetch.io.id_instruction
if2id.io.instruction_address := inst_fetch.io.instruction_address
if2id.io.interrupt_flag := io.interrupt_flag
id.io.instruction := if2id.io.output_instruction
id2ex.io.instruction := if2id.io.output_instruction
id2ex.io.instruction_address := if2id.io.output_instruction_address
id2ex.io.reg1_data := regs.io.read_data1
id2ex.io.reg2_data := regs.io.read_data2
id2ex.io.regs_write_enable := id.io.ex_reg_write_enable
id2ex.io.regs_write_address := id.io.ex_reg_write_address
id2ex.io.regs_write_source := id.io.ex_reg_write_source
id2ex.io.immediate := id.io.ex_immediate
id2ex.io.aluop1_source := id.io.ex_aluop1_source
id2ex.io.aluop2_source := id.io.ex_aluop2_source
id2ex.io.csr_write_enable := id.io.ex_csr_write_enable
id2ex.io.csr_address := id.io.ex_csr_address
id2ex.io.memory_read_enable := id.io.ex_memory_read_enable
id2ex.io.memory_write_enable := id.io.ex_memory_write_enable
id2ex.io.csr_read_data := csr_regs.io.id_reg_read_data
ex.io.instruction := id2ex.io.output_instruction
ex.io.instruction_address := id2ex.io.output_instruction_address
ex.io.reg1_data := id2ex.io.output_reg1_data
ex.io.reg2_data := id2ex.io.output_reg2_data
ex.io.csr_read_data := id2ex.io.output_csr_read_data
ex.io.immediate_id := id2ex.io.output_immediate
ex.io.aluop1_source_id := id2ex.io.output_aluop1_source
ex.io.aluop2_source_id := id2ex.io.output_aluop2_source
ex.io.memory_read_enable_id := id2ex.io.output_memory_read_enable
ex.io.memory_write_enable_id := id2ex.io.output_memory_write_enable
ex.io.regs_write_source_id := id2ex.io.output_regs_write_source
ex.io.interrupt_assert_clint := clint.io.ex_interrupt_assert
ex.io.interrupt_handler_address_clint := clint.io.ex_interrupt_handler_address
io.device_select := ex.io.memory_bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
io.memory_bundle <> ex.io.memory_bundle
io.memory_bundle.address := 0.U(Parameters.SlaveDeviceCountBits.W) ## ex.io.memory_bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0)
clint.io.instruction_address_if := inst_fetch.io.instruction_address
clint.io.instruction_address_id := if2id.io.output_instruction_address
clint.io.instruction_ex := id2ex.io.output_instruction
clint.io.jump_flag := ex.io.clint_jump_flag
clint.io.jump_address := ex.io.clint_jump_address
clint.io.interrupt_flag := if2id.io.output_interrupt_flag
clint.io.csr_bundle <> csr_regs.io.clint_access_bundle
csr_regs.io.reg_read_address_id := id.io.ex_csr_address
csr_regs.io.reg_write_enable_ex := id2ex.io.output_csr_write_enable
csr_regs.io.reg_write_address_ex := id2ex.io.output_csr_address
csr_regs.io.reg_write_data_ex := ex.io.csr_write_data
}

21
lab3/src/main/scala/riscv/core/threestage/Control.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
class Control extends Module {
// Lab3(Flush)
}

191
lab3/src/main/scala/riscv/core/threestage/Execute.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import chisel3.util._
import peripheral.RAMBundle
import riscv.Parameters
import riscv.core.{ALU, ALUControl}
class Execute extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val csr_read_data = Input(UInt(Parameters.DataWidth))
val immediate_id = Input(UInt(Parameters.DataWidth))
val aluop1_source_id = Input(UInt(1.W))
val aluop2_source_id = Input(UInt(1.W))
val memory_read_enable_id = Input(Bool())
val memory_write_enable_id = Input(Bool())
val regs_write_source_id = Input(UInt(2.W))
val interrupt_assert_clint = Input(Bool())
val interrupt_handler_address_clint = Input(UInt(Parameters.AddrWidth))
val memory_bundle = Flipped(new RAMBundle)
val csr_write_data = Output(UInt(Parameters.DataWidth))
val regs_write_data = Output(UInt(Parameters.DataWidth))
val if_jump_flag = Output(Bool())
val if_jump_address = Output(UInt(Parameters.AddrWidth))
val clint_jump_flag = Output(Bool())
val clint_jump_address = Output(UInt(Parameters.AddrWidth))
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val uimm = io.instruction(19, 15)
// ALU compute
val alu = Module(new ALU)
val alu_ctrl = Module(new ALUControl)
alu_ctrl.io.opcode := opcode
alu_ctrl.io.funct3 := funct3
alu_ctrl.io.funct7 := funct7
alu.io.func := alu_ctrl.io.alu_funct
alu.io.op1 := Mux(
io.aluop1_source_id === ALUOp1Source.InstructionAddress,
io.instruction_address,
io.reg1_data
)
alu.io.op2 := Mux(
io.aluop2_source_id === ALUOp2Source.Immediate,
io.immediate_id,
io.reg2_data
)
io.csr_write_data := MuxLookup(
funct3,
0.U,
IndexedSeq(
InstructionsTypeCSR.csrrw -> io.reg1_data,
InstructionsTypeCSR.csrrc -> (io.csr_read_data & (~io.reg1_data).asUInt),
InstructionsTypeCSR.csrrs -> (io.csr_read_data | io.reg1_data),
InstructionsTypeCSR.csrrwi -> (0.U(27.W) ## uimm),
InstructionsTypeCSR.csrrci -> (io.csr_read_data & (~(0.U(27.W) ## uimm)).asUInt),
InstructionsTypeCSR.csrrsi -> (io.csr_read_data | 0.U(27.W) ## uimm),
)
)
// memory access
val mem_address_index = alu.io.result(log2Up(Parameters.WordSize) - 1, 0).asUInt
val mem_read_data = Wire(UInt(Parameters.DataWidth))
io.memory_bundle.write_enable := io.memory_write_enable_id
io.memory_bundle.write_data := 0.U
io.memory_bundle.address := alu.io.result
io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
mem_read_data := 0.U
when(io.memory_read_enable_id) {
val data = io.memory_bundle.read_data
mem_read_data := MuxLookup(
funct3,
0.U,
IndexedSeq(
InstructionsTypeL.lb -> MuxLookup(
mem_address_index,
Cat(Fill(24, data(31)), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
2.U -> Cat(Fill(24, data(23)), data(23, 16))
)
),
InstructionsTypeL.lbu -> MuxLookup(
mem_address_index,
Cat(Fill(24, 0.U), data(31, 24)),
IndexedSeq(
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
2.U -> Cat(Fill(24, 0.U), data(23, 16))
)
),
InstructionsTypeL.lh -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, data(15)), data(15, 0)),
Cat(Fill(16, data(31)), data(31, 16))
),
InstructionsTypeL.lhu -> Mux(
mem_address_index === 0.U,
Cat(Fill(16, 0.U), data(15, 0)),
Cat(Fill(16, 0.U), data(31, 16))
),
InstructionsTypeL.lw -> data
)
)
}.elsewhen(io.memory_write_enable_id) {
io.memory_bundle.write_data := io.reg2_data
io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
when(funct3 === InstructionsTypeS.sb) {
io.memory_bundle.write_strobe(mem_address_index) := true.B
io.memory_bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
}.elsewhen(funct3 === InstructionsTypeS.sh) {
when(mem_address_index === 0.U) {
for (i <- 0 until Parameters.WordSize / 2) {
io.memory_bundle.write_strobe(i) := true.B
}
io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
}.otherwise {
for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
io.memory_bundle.write_strobe(i) := true.B
}
io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
.WordSize / 2 * Parameters.ByteBits)
}
}.elsewhen(funct3 === InstructionsTypeS.sw) {
for (i <- 0 until Parameters.WordSize) {
io.memory_bundle.write_strobe(i) := true.B
}
}
}
// write back
io.regs_write_data := MuxLookup(
io.regs_write_source_id,
alu.io.result,
IndexedSeq(
RegWriteSource.Memory -> mem_read_data,
RegWriteSource.CSR -> io.csr_read_data,
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
)
)
// jump and interrupt
val instruction_jump_flag = (opcode === Instructions.jal) ||
(opcode === Instructions.jalr) ||
(opcode === InstructionTypes.B) && MuxLookup(
funct3,
false.B,
IndexedSeq(
InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
InstructionsTypeB.blt -> (io.reg1_data.asSInt < io.reg2_data.asSInt),
InstructionsTypeB.bge -> (io.reg1_data.asSInt >= io.reg2_data.asSInt),
InstructionsTypeB.bltu -> (io.reg1_data.asUInt < io.reg2_data.asUInt),
InstructionsTypeB.bgeu -> (io.reg1_data.asUInt >= io.reg2_data.asUInt)
)
)
io.clint_jump_flag := instruction_jump_flag
io.clint_jump_address := alu.io.result
io.if_jump_flag := io.interrupt_assert_clint || instruction_jump_flag
io.if_jump_address := Mux(io.interrupt_assert_clint,
io.interrupt_handler_address_clint,
alu.io.result
)
}

148
lab3/src/main/scala/riscv/core/threestage/ID2EX.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class ID2EX extends Module {
val io = IO(new Bundle {
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val regs_write_enable = Input(Bool())
val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_write_source = Input(UInt(2.W))
val reg1_data = Input(UInt(Parameters.DataWidth))
val reg2_data = Input(UInt(Parameters.DataWidth))
val immediate = Input(UInt(Parameters.DataWidth))
val aluop1_source = Input(UInt(1.W))
val aluop2_source = Input(UInt(1.W))
val csr_write_enable = Input(Bool())
val csr_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
val memory_read_enable = Input(Bool())
val memory_write_enable = Input(Bool())
val csr_read_data = Input(UInt(Parameters.DataWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_regs_write_enable = Output(Bool())
val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val output_regs_write_source = Output(UInt(2.W))
val output_reg1_data = Output(UInt(Parameters.DataWidth))
val output_reg2_data = Output(UInt(Parameters.DataWidth))
val output_immediate = Output(UInt(Parameters.DataWidth))
val output_aluop1_source = Output(UInt(1.W))
val output_aluop2_source = Output(UInt(1.W))
val output_csr_write_enable = Output(Bool())
val output_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val output_memory_read_enable = Output(Bool())
val output_memory_write_enable = Output(Bool())
val output_csr_read_data = Output(UInt(Parameters.DataWidth))
})
val stall = false.B
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val regs_write_enable = Module(new PipelineRegister(1))
regs_write_enable.io.in := io.regs_write_enable
regs_write_enable.io.stall := stall
regs_write_enable.io.flush := io.flush
io.output_regs_write_enable := regs_write_enable.io.out
val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits))
regs_write_address.io.in := io.regs_write_address
regs_write_address.io.stall := stall
regs_write_address.io.flush := io.flush
io.output_regs_write_address := regs_write_address.io.out
val regs_write_source = Module(new PipelineRegister(2))
regs_write_source.io.in := io.regs_write_source
regs_write_source.io.stall := stall
regs_write_source.io.flush := io.flush
io.output_regs_write_source := regs_write_source.io.out
val reg1_data = Module(new PipelineRegister())
reg1_data.io.in := io.reg1_data
reg1_data.io.stall := stall
reg1_data.io.flush := io.flush
io.output_reg1_data := reg1_data.io.out
val reg2_data = Module(new PipelineRegister())
reg2_data.io.in := io.reg2_data
reg2_data.io.stall := stall
reg2_data.io.flush := io.flush
io.output_reg2_data := reg2_data.io.out
val immediate = Module(new PipelineRegister())
immediate.io.in := io.immediate
immediate.io.stall := stall
immediate.io.flush := io.flush
io.output_immediate := immediate.io.out
val aluop1_source = Module(new PipelineRegister(1))
aluop1_source.io.in := io.aluop1_source
aluop1_source.io.stall := stall
aluop1_source.io.flush := io.flush
io.output_aluop1_source := aluop1_source.io.out
val aluop2_source = Module(new PipelineRegister(1))
aluop2_source.io.in := io.aluop2_source
aluop2_source.io.stall := stall
aluop2_source.io.flush := io.flush
io.output_aluop2_source := aluop2_source.io.out
val csr_write_enable = Module(new PipelineRegister(1))
csr_write_enable.io.in := io.csr_write_enable
csr_write_enable.io.stall := stall
csr_write_enable.io.flush := io.flush
io.output_csr_write_enable := csr_write_enable.io.out
val csr_address = Module(new PipelineRegister(Parameters.CSRRegisterAddrBits))
csr_address.io.in := io.csr_address
csr_address.io.stall := stall
csr_address.io.flush := io.flush
io.output_csr_address := csr_address.io.out
val memory_read_enable = Module(new PipelineRegister(1))
memory_read_enable.io.in := io.memory_read_enable
memory_read_enable.io.stall := stall
memory_read_enable.io.flush := io.flush
io.output_memory_read_enable := memory_read_enable.io.out
val memory_write_enable = Module(new PipelineRegister(1))
memory_write_enable.io.in := io.memory_write_enable
memory_write_enable.io.stall := stall
memory_write_enable.io.flush := io.flush
io.output_memory_write_enable := memory_write_enable.io.out
val csr_read_data = Module(new PipelineRegister())
csr_read_data.io.in := io.csr_read_data
csr_read_data.io.stall := stall
csr_read_data.io.flush := io.flush
io.output_csr_read_data := csr_read_data.io.out
}

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lab3/src/main/scala/riscv/core/threestage/IF2ID.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import riscv.Parameters
import riscv.core.PipelineRegister
class IF2ID extends Module {
val io = IO(new Bundle {
val flush = Input(Bool())
val instruction = Input(UInt(Parameters.InstructionWidth))
val instruction_address = Input(UInt(Parameters.AddrWidth))
val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
val output_instruction = Output(UInt(Parameters.DataWidth))
val output_instruction_address = Output(UInt(Parameters.AddrWidth))
val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth))
})
val stall = false.B
val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop))
instruction.io.in := io.instruction
instruction.io.stall := stall
instruction.io.flush := io.flush
io.output_instruction := instruction.io.out
val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress))
instruction_address.io.in := io.instruction_address
instruction_address.io.stall := stall
instruction_address.io.flush := io.flush
io.output_instruction_address := instruction_address.io.out
val interrupt_flag = Module(new PipelineRegister(Parameters.InterruptFlagBits))
interrupt_flag.io.in := io.interrupt_flag
interrupt_flag.io.stall := stall
interrupt_flag.io.flush := io.flush
io.output_interrupt_flag := interrupt_flag.io.out
}

207
lab3/src/main/scala/riscv/core/threestage/InstructionDecode.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import chisel3.util._
import riscv.Parameters
object InstructionTypes {
val L = "b0000011".U
val I = "b0010011".U
val S = "b0100011".U
val RM = "b0110011".U
val B = "b1100011".U
}
object Instructions {
val lui = "b0110111".U
val nop = "b0000001".U
val jal = "b1101111".U
val jalr = "b1100111".U
val auipc = "b0010111".U
val csr = "b1110011".U
val fence = "b0001111".U
}
object InstructionsTypeL {
val lb = "b000".U
val lh = "b001".U
val lw = "b010".U
val lbu = "b100".U
val lhu = "b101".U
}
object InstructionsTypeI {
val addi = 0.U
val slli = 1.U
val slti = 2.U
val sltiu = 3.U
val xori = 4.U
val sri = 5.U
val ori = 6.U
val andi = 7.U
}
object InstructionsTypeS {
val sb = "b000".U
val sh = "b001".U
val sw = "b010".U
}
object InstructionsTypeR {
val add_sub = 0.U
val sll = 1.U
val slt = 2.U
val sltu = 3.U
val xor = 4.U
val sr = 5.U
val or = 6.U
val and = 7.U
}
object InstructionsTypeM {
val mul = 0.U
val mulh = 1.U
val mulhsu = 2.U
val mulhum = 3.U
val div = 4.U
val divu = 5.U
val rem = 6.U
val remu = 7.U
}
object InstructionsTypeB {
val beq = "b000".U
val bne = "b001".U
val blt = "b100".U
val bge = "b101".U
val bltu = "b110".U
val bgeu = "b111".U
}
object InstructionsTypeCSR {
val csrrw = "b001".U
val csrrs = "b010".U
val csrrc = "b011".U
val csrrwi = "b101".U
val csrrsi = "b110".U
val csrrci = "b111".U
}
object InstructionsNop {
val nop = 0x00000013L.U(Parameters.DataWidth)
}
object InstructionsRet {
val mret = 0x30200073L.U(Parameters.DataWidth)
val ret = 0x00008067L.U(Parameters.DataWidth)
}
object InstructionsEnv {
val ecall = 0x00000073L.U(Parameters.DataWidth)
val ebreak = 0x00100073L.U(Parameters.DataWidth)
}
object ALUOp1Source {
val Register = 0.U(1.W)
val InstructionAddress = 1.U(1.W)
}
object ALUOp2Source {
val Register = 0.U(1.W)
val Immediate = 1.U(1.W)
}
object RegWriteSource {
val ALUResult = 0.U(2.W)
val Memory = 1.U(2.W)
val CSR = 2.U(2.W)
val NextInstructionAddress = 3.U(2.W)
}
class InstructionDecode extends Module {
val io = IO(new Bundle {
val instruction = Input(UInt(Parameters.InstructionWidth))
val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_immediate = Output(UInt(Parameters.DataWidth))
val ex_aluop1_source = Output(Bool())
val ex_aluop2_source = Output(Bool())
val ex_memory_read_enable = Output(Bool())
val ex_memory_write_enable = Output(Bool())
val ex_reg_write_source = Output(UInt(2.W))
val ex_reg_write_enable = Output(Bool())
val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
val ex_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth))
val ex_csr_write_enable = Output(Bool())
})
val opcode = io.instruction(6, 0)
val funct3 = io.instruction(14, 12)
val funct7 = io.instruction(31, 25)
val rd = io.instruction(11, 7)
val rs1 = io.instruction(19, 15)
val rs2 = io.instruction(24, 20)
io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
io.regs_reg2_read_address := rs2
io.ex_immediate := MuxLookup(
opcode,
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
IndexedSeq(
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
)
)
io.ex_aluop1_source := Mux(
opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
ALUOp1Source.InstructionAddress,
ALUOp1Source.Register
)
io.ex_aluop2_source := Mux(
opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
io.ex_memory_read_enable := opcode === InstructionTypes.L
io.ex_memory_write_enable := opcode === InstructionTypes.S
io.ex_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult,
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.csr -> RegWriteSource.CSR,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)
io.ex_reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
(opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr)
io.ex_reg_write_address := rd
io.ex_csr_address := io.instruction(31, 20)
io.ex_csr_write_enable := (opcode === Instructions.csr) && (
funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi ||
funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi ||
funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci
)
}

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lab3/src/main/scala/riscv/core/threestage/InstructionFetch.scala Normal file
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// Copyright 2021 Howard Lau
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package riscv.core.threestage
import chisel3._
import chisel3.util.MuxCase
import riscv.Parameters
object ProgramCounter {
val EntryAddress = Parameters.EntryAddress
}
class InstructionFetch extends Module {
val io = IO(new Bundle {
val jump_flag_ex = Input(Bool())
val jump_address_ex = Input(UInt(Parameters.AddrWidth))
val rom_instruction = Input(UInt(Parameters.DataWidth))
val instruction_valid = Input(Bool())
val instruction_address = Output(UInt(Parameters.AddrWidth))
val id_instruction = Output(UInt(Parameters.InstructionWidth))
})
val pc = RegInit(ProgramCounter.EntryAddress)
pc := MuxCase(
pc,
IndexedSeq(
io.jump_flag_ex -> io.jump_address_ex,
io.instruction_valid -> (pc + 4.U)
)
)
io.instruction_address := pc
io.id_instruction := Mux(io.instruction_valid, io.rom_instruction, InstructionsNop.nop)
}