init repo

lab2/src/test/scala/riscv/TestAnnotations.scala

@@ -0,0 +1,52 @@
+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
+import firrtl.AnnotationSeq
+
+import java.nio.file.{Files, Paths}
+
+object VerilatorEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("Path")) {
+    if (sys.env.getOrElse("Path", "").split(";").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  } else {
+    if (sys.env.getOrElse("PATH", "").split(":").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  }
+}
+
+object WriteVcdEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("WRITE_VCD")) {
+    Seq(WriteVcdAnnotation)
+  } else {
+    Seq()
+  }
+}
+
+object TestAnnotations {
+  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+}

lab2/src/test/scala/riscv/singlecycle/CLINTCSRTest.scala

@@ -0,0 +1,142 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.{Parameters, TestAnnotations}
+import riscv.core.{ALUOp1Source, ALUOp2Source, CLINT, CSR, CSRRegister, InstructionDecode, InstructionsNop, InstructionsRet}
+
+class CLINTCSRTestTopModule extends Module {
+  val io = IO( new Bundle{
+    val csr_regs_debug_read_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
+    val csr_regs_write_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
+    val csr_regs_write_data = Input(UInt(Parameters.DataWidth))
+    val csr_regs_write_enable = Input(Bool())
+    val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
+    val instruction = Input(UInt(Parameters.DataWidth))
+    val instruction_address = Input(UInt(Parameters.AddrWidth))
+
+    val jump_flag = Input(Bool())
+    val jump_address = Input(UInt(Parameters.AddrWidth))
+
+    val interrupt_assert = Output(Bool())
+    val interrupt_handler_address = Output(UInt(Parameters.DataWidth))
+    val csr_regs_read_data = Output(UInt(Parameters.DataWidth))
+    val csr_regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+  val csr_regs = Module(new CSR)
+  val clint = Module(new CLINT)
+
+  clint.io.instruction := io.instruction
+  clint.io.instruction_address := io.instruction_address
+  clint.io.interrupt_flag := io.interrupt_flag
+  clint.io.jump_flag := io.jump_flag
+  clint.io.jump_address := io.jump_address
+
+  io.interrupt_handler_address := clint.io.interrupt_handler_address
+  io.interrupt_assert := clint.io.interrupt_assert
+  io.csr_regs_read_data := csr_regs.io.reg_read_data
+  csr_regs.io.reg_write_address_id := io.csr_regs_write_address
+  csr_regs.io.debug_reg_read_address := io.csr_regs_debug_read_address
+  csr_regs.io.reg_write_data_ex := io.csr_regs_write_data
+  csr_regs.io.reg_write_enable_id := io.csr_regs_write_enable
+  csr_regs.io.reg_read_address_id := io.csr_regs_write_address
+  io.csr_regs_debug_read_data := csr_regs.io.debug_reg_read_data
+
+  csr_regs.io.clint_access_bundle <> clint.io.csr_bundle
+
+}
+
+class CLINTCSRTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "CLINTCSRTest of Single Cycle CPU"
+  it should "process " in {
+    test(new CLINTCSRTestTopModule).withAnnotations(TestAnnotations.annos) { c =>
+
+      //
+      c.io.jump_flag.poke(false.B)
+      c.io.csr_regs_write_enable.poke(false.B)
+      c.io.interrupt_flag.poke(0.U)
+      c.clock.step()
+      c.io.csr_regs_write_enable.poke(true.B)
+      c.io.csr_regs_write_address.poke(CSRRegister.MTVEC)
+      c.io.csr_regs_write_data.poke(0x1144L.U)
+      c.clock.step()
+      c.io.csr_regs_write_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_write_data.poke(0x1888L.U)
+      c.clock.step()
+      c.io.csr_regs_write_enable.poke(false.B)
+      //handle interrupt when not jumping
+      c.io.jump_flag.poke(false.B)
+      c.io.instruction_address.poke(0x1900L.U)
+      c.io.instruction.poke(InstructionsNop.nop)
+      c.io.interrupt_flag.poke(1.U)
+      c.io.interrupt_assert.expect(true.B)
+      c.io.interrupt_handler_address.expect(0x1144L.U)
+      c.clock.step()
+      c.io.interrupt_flag.poke(0.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MEPC)
+      c.io.csr_regs_debug_read_data.expect(0x1904L.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MCAUSE)
+      c.io.csr_regs_debug_read_data.expect(0x80000007L.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_debug_read_data.expect(0x1880L.U)
+
+      c.clock.step(25)
+
+      //mret from interrupt handler
+      c.io.instruction.poke(InstructionsRet.mret)
+      c.io.interrupt_assert.expect(true.B)
+      c.io.interrupt_handler_address.expect(0x1904L.U)
+      c.clock.step()
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_debug_read_data.expect(0x1888L.U)
+
+      //handle interrupt when jumping
+      c.io.jump_flag.poke(true.B)
+      c.io.jump_address.poke(0x1990L.U)
+      c.io.interrupt_flag.poke(2.U)
+      c.io.interrupt_assert.expect(true.B)
+      c.io.interrupt_handler_address.expect(0x1144L.U)
+      c.clock.step()
+      c.io.interrupt_flag.poke(0.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MEPC)
+      c.io.csr_regs_debug_read_data.expect(0x1990L.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MCAUSE)
+      c.io.csr_regs_debug_read_data.expect(0x8000000BL.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_debug_read_data.expect(0x1880L.U)
+
+      c.clock.step(25)
+
+      //mret from interrupt handler
+      c.io.instruction.poke(InstructionsRet.mret)
+      c.io.interrupt_assert.expect(true.B)
+      c.io.interrupt_handler_address.expect(0x1990L.U)
+      c.clock.step()
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_debug_read_data.expect(0x1888L.U)
+      c.io.instruction.poke(InstructionsNop.nop)
+
+      //don't handle interrupt under certain situation
+      c.io.csr_regs_write_enable.poke(true.B)
+      c.io.csr_regs_write_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_write_data.poke(0x1880L.U)
+      c.io.interrupt_flag.poke(1.U)
+      c.io.interrupt_assert.expect(false.B)
+    }
+  }
+}

lab2/src/test/scala/riscv/singlecycle/CPUTest.scala

@@ -0,0 +1,162 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import board.basys3.BootStates
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import peripheral.{InstructionROM, Memory, ROMLoader}
+import riscv.core.{CPU, CSRRegister, ProgramCounter}
+import riscv.{Parameters, TestAnnotations}
+
+import java.nio.{ByteBuffer, ByteOrder}
+
+
+class TestTopModule(exeFilename: String) extends Module {
+  val io = IO(new Bundle {
+    val mem_debug_read_address = Input(UInt(Parameters.AddrWidth))
+    val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val csr_regs_debug_read_address = Input(UInt(Parameters.CSRRegisterAddrWidth))
+    val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth))
+
+
+    val regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val mem_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val csr_regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val pc_debug_read = Output(UInt(Parameters.AddrWidth));
+  })
+
+  val mem = Module(new Memory(8192))
+  val instruction_rom = Module(new InstructionROM(exeFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+    cpu.io.interrupt_flag := io.interrupt_flag
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      cpu.io.memory_bundle <> mem.io.bundle
+    }
+
+    cpu.io.regs_debug_read_address := io.regs_debug_read_address
+    cpu.io.csr_regs_debug_read_address := io.csr_regs_debug_read_address
+    io.regs_debug_read_data := cpu.io.regs_debug_read_data
+    io.csr_regs_debug_read_data := cpu.io.csr_regs_debug_read_data
+    io.pc_debug_read := cpu.io.instruction_address
+  }
+
+  mem.io.debug_read_address := io.mem_debug_read_address
+  io.mem_debug_read_data := mem.io.debug_read_data
+}
+
+
+class FibonacciTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU with CSR and CLINT"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+}
+
+class QuicksortTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU with CSR and CLINT"
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+}
+
+class ByteAccessTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU with CSR and CLINT"
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 500) {
+        c.clock.step()
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+}
+
+class SimpleTrapTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU with CSR and CLINT"
+  it should "jump to trap handler and then return" in {
+    test(new TestTopModule("simpletest.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 1000) {
+        c.clock.step()
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.interrupt_flag.poke(0x1.U)
+      c.clock.step(5)
+      c.io.interrupt_flag.poke(0.U)
+      for (i <- 1 to 1000) {
+        c.clock.step()
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MSTATUS)
+      c.io.csr_regs_debug_read_data.expect(0x1888.U)
+      c.io.csr_regs_debug_read_address.poke(CSRRegister.MCAUSE)
+      c.io.csr_regs_debug_read_data.expect(0x80000007L.U)
+      c.io.mem_debug_read_address.poke(0x4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(0x2022L.U)
+    }
+  }
+}

lab2/src/test/scala/riscv/singlecycle/ExecuteTest.scala

@@ -0,0 +1,49 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.Execute
+
+class ExecuteTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "CLINTCSRTest of Single Cycle CPU"
+  it should "produce correct data for csr write" in {
+    test(new Execute).withAnnotations(TestAnnotations.annos) { c =>
+      c.io.instruction.poke(0x30047073L.U) // csrc mstatus,3
+      c.io.csr_reg_read_data.poke(0x1888L.U)
+      c.io.reg1_data.poke(0x1880L.U)
+      c.io.csr_reg_write_data.expect(0x1880.U)
+      c.clock.step()
+      c.io.instruction.poke(0x30046073L.U) //csrs mastatus,3
+      c.io.csr_reg_read_data.poke(0x1880L.U)
+      c.io.reg1_data.poke(0x1880L.U)
+      c.io.csr_reg_write_data.expect(0x1888.U)
+      c.clock.step()
+      c.io.instruction.poke(0x30051073L.U) //csrw mstatus, a0
+      c.io.csr_reg_read_data.poke(0.U)
+      c.io.reg1_data.poke(0x1888L.U)
+      c.io.csr_reg_write_data.expect(0x1888.U)
+      c.clock.step()
+      c.io.instruction.poke(0x30002573L.U) //csrr a0, mstatus
+      c.io.csr_reg_read_data.poke(0x1888.U)
+      c.io.reg1_data.poke(0x0L.U)
+      c.io.csr_reg_write_data.expect(0x1888.U)
+      c.clock.step()
+    }
+  }
+}

lab2/src/test/scala/riscv/singlecycle/TimerTest.scala

@@ -0,0 +1,61 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.{Parameters, TestAnnotations}
+import peripheral.{RAMBundle, Timer}
+
+class TimerTest extends AnyFlatSpec with ChiselScalatestTester {
+
+  class TestTimer extends Module {
+    val io = IO(new Bundle {
+      val debug_limit = Output(UInt(Parameters.DataWidth))
+      val debug_enabled = Output(Bool())
+      val bundle = new RAMBundle
+
+      val write_strobe = Input(UInt(4.W))
+    })
+    val timer = Module(new Timer)
+    io.debug_limit := timer.io.debug_limit
+    io.debug_enabled := timer.io.debug_enabled
+
+    timer.io.bundle <> io.bundle
+    timer.io.bundle.write_strobe := VecInit(io.write_strobe.asBools)
+  }
+
+  behavior of "Timer"
+  it should "read and write the limit" in {
+    test(new TestTimer).withAnnotations(TestAnnotations.annos) {c =>
+      c.io.write_strobe.poke(0xF.U)
+      c.io.bundle.write_enable.poke(true.B)
+      c.io.bundle.address.poke(0x4.U)
+      c.io.bundle.write_data.poke(0x990315.U)
+      c.clock.step()
+      c.io.bundle.write_enable.poke(false.B)
+      c.clock.step()
+      c.io.debug_limit.expect(0x990315.U)
+      c.io.bundle.write_enable.poke(true.B)
+      c.io.bundle.address.poke(0x8.U)
+      c.io.bundle.write_data.poke(0.U)
+      c.clock.step()
+      c.io.bundle.write_enable.poke(false.B)
+      c.io.debug_enabled.expect(false.B)
+    }
+  }
+}
+