init repo

lab2/riscv-target/yatcpu/Makefile.include

@@ -0,0 +1,7 @@
+export TARGETDIR ?= riscv-target
+export XLEN = 32
+export RISCV_TARGET = yatcpu
+export RISCV_DEVICE = 
+export RISCV_TARGET_FLAGS = 
+export RISCV_ASSERT = 0
+JOBS = -j1

lab2/riscv-target/yatcpu/device/rv32i_m/I/Makefile.include

@@ -0,0 +1,54 @@
+TARGET_SIM ?= verilog/verilator/obj_dir/VTop
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+
+OBJDUMP_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug; \
+                    $$(RISCV_OBJDUMP) -t $$@ | grep " begin_signature$$$$" | awk '{ print $$$$1 }' > $$@.begin_signature; \
+                    $$(RISCV_OBJDUMP) -t $$@ | grep " end_signature$$$$" | awk '{ print $$$$1 }' > $$@.end_signature; \
+                    $$(RISCV_OBJDUMP) -t $$@ | grep " tohost$$$$" | awk '{ print $$$$1 }' > $$@.halt \
+
+
+OBJCOPY_CMD = $$(RISCV_OBJCOPY) $$@ -O binary  -j .text -j .data -j .tohost $$@.asmbin
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJDUMP_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+                $(OBJCOPY_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJCOPY) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+    
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) \
+            -signature 0x$(shell cat $(<).begin_signature) 0x$(shell cat $(<).end_signature) $(*).signature.output \
+            -halt 0x$(shell cat $(<).halt) \
+            -time 1000000 \
+            -instruction $(<).asmbin
+RUN_TARGET = \
+    $(RUN_CMD)

lab2/riscv-target/yatcpu/link.ld

@@ -0,0 +1,12 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(rvtest_entry_point)
+
+SECTIONS
+{
+  . = 0x00001000;
+  .text : { *(.text.init) *(.text.startup) *(.text) }
+  .data ALIGN(0x1000) : { *(.data*) *(.rodata*) *(.sdata*) }
+  .tohost ALIGN(0x1000) : { *(.tohost) }
+  .bss : { *(.bss) }
+  _end = .;
+}

lab2/riscv-target/yatcpu/model_test.h

@@ -0,0 +1,46 @@
+#ifndef _COMPLIANCE_MODEL_H_
+#define _COMPLIANCE_MODEL_H_
+
+#define ALIGNMENT 2
+
+#define RVMODEL_DATA_SECTION \
+    .pushsection .tohost,"aw",@progbits; \
+    .align 4; .global tohost; tohost: .word 0; \
+    .popsection;
+
+#define RVMODEL_BOOT
+
+#define RVMODEL_HALT \
+    li x1, 0xBABECAFE; \
+    write_tohost: \
+        sw x1, tohost, x0; \
+    loop: j loop
+
+//RV_COMPLIANCE_DATA_BEGIN
+#define RVMODEL_DATA_BEGIN                                              \
+  .align 4; .global begin_signature; begin_signature:
+
+//RV_COMPLIANCE_DATA_END
+#define RVMODEL_DATA_END                                                      \
+  .align 4; .global end_signature; end_signature:  \
+  RVMODEL_DATA_SECTION                                                        \
+
+//RVTEST_IO_INIT
+#define RVMODEL_IO_INIT
+//RVTEST_IO_WRITE_STR
+#define RVMODEL_IO_WRITE_STR(_R, _STR)
+//RVTEST_IO_CHECK
+#define RVMODEL_IO_CHECK()
+//RVTEST_IO_ASSERT_GPR_EQ
+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
+//RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+//RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#define RVMODEL_SET_MSW_INT
+#define RVMODEL_CLEAR_MSW_INT
+#define RVMODEL_CLEAR_MTIMER_INT
+#define RVMODEL_CLEAR_MEXT_INT
+
+#endif