init repo

lab1/verilog/basys3/test.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/12/17 16:31:05
+// Design Name: 
+// Module Name: test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module test();
+reg clock;
+reg reset;
+initial begin
+clock = 0;
+forever #1 clock = ~clock;
+end
+initial begin
+reset = 1;
+#2 reset = 0;
+end
+Top top(clock, reset);
+endmodule