diff --git a/lab1/src/main/scala/board/z710/Top.scala b/lab1/src/main/scala/board/z710/Top.scala index 0f11ea2..8b3138c 100644 --- a/lab1/src/main/scala/board/z710/Top.scala +++ b/lab1/src/main/scala/board/z710/Top.scala @@ -37,7 +37,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { // val hdmi_display = Module(new HDMIDisplay) // val display = Module(new CharacterDisplay) // val timer = Module(new Timer) - val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error + val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) val dummy = Module(new Dummy) // display.io.bundle <> dummy.io.bundle @@ -58,7 +58,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { val CPU_clkdiv = RegInit(UInt(2.W),0.U) val CPU_tick = Wire(Bool()) val CPU_next = Wire(UInt(2.W)) - CPU_next := Mux(CPU_clkdiv === 9.U, 0.U, CPU_clkdiv + 1.U) + CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U) CPU_tick := CPU_clkdiv === 0.U CPU_clkdiv := CPU_next diff --git a/lab2/src/main/scala/board/z710/Top.scala b/lab2/src/main/scala/board/z710/Top.scala index 97864a5..57398ff 100644 --- a/lab2/src/main/scala/board/z710/Top.scala +++ b/lab2/src/main/scala/board/z710/Top.scala @@ -32,7 +32,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { // val hdmi_display = Module(new HDMIDisplay) // val display = Module(new CharacterDisplay) val timer = Module(new Timer) - val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error + val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) val dummy = Module(new Dummy) // display.io.bundle <> dummy.io.bundle diff --git a/lab2/src/main/scala/board/z710v1.3/Top.scala b/lab2/src/main/scala/board/z710v1.3/Top.scala index bd52382..4cf7f15 100644 --- a/lab2/src/main/scala/board/z710v1.3/Top.scala +++ b/lab2/src/main/scala/board/z710v1.3/Top.scala @@ -36,7 +36,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { // val hdmi_display = Module(new HDMIDisplay) // val display = Module(new CharacterDisplay) val timer = Module(new Timer) - val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error + val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) val dummy = Module(new Dummy) // display.io.bundle <> dummy.io.bundle diff --git a/lab3/src/main/scala/board/z710/Top.scala b/lab3/src/main/scala/board/z710/Top.scala index a84ab33..7b9ee16 100644 --- a/lab3/src/main/scala/board/z710/Top.scala +++ b/lab3/src/main/scala/board/z710/Top.scala @@ -36,7 +36,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { // val hdmi_display = Module(new HDMIDisplay) // val display = Module(new CharacterDisplay) val timer = Module(new Timer) - val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error + val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) val dummy = Module(new Dummy) // display.io.bundle <> dummy.io.bundle diff --git a/lab3/src/main/scala/board/z710v1.3/Top.scala b/lab3/src/main/scala/board/z710v1.3/Top.scala new file mode 100644 index 0000000..7496126 --- /dev/null +++ b/lab3/src/main/scala/board/z710v1.3/Top.scala @@ -0,0 +1,103 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.z710v1_3 + +import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.util.Cat +import peripheral._ +import riscv.Parameters +import riscv.core.CPU + +class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module { + val io = IO(new Bundle() { + val tx = Output(Bool()) + val rx = Input(Bool()) + + val led = Output(Bool()) + }) + + val clock_freq = 50_000_000 + + val mem = Module(new Memory(Parameters.MemorySizeInWords)) + // val hdmi_display = Module(new HDMIDisplay) + // val display = Module(new CharacterDisplay) + val timer = Module(new Timer) + val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) + val dummy = Module(new Dummy) + + // display.io.bundle <> dummy.io.bundle + mem.io.bundle <> dummy.io.bundle + mem.io.debug_read_address := 0.U + timer.io.bundle <> dummy.io.bundle + uart.io.bundle <> dummy.io.bundle + io.tx := uart.io.txd + uart.io.rxd := io.rx + + val instruction_rom = Module(new InstructionROM(binaryFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + + rom_loader.io.rom_data := instruction_rom.io.data + rom_loader.io.load_address := Parameters.EntryAddress + instruction_rom.io.address := rom_loader.io.rom_address + + val CPU_clkdiv = RegInit(UInt(2.W),0.U) + val CPU_tick = Wire(Bool()) + val CPU_next = Wire(UInt(2.W)) + CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U) + CPU_tick := CPU_clkdiv === 0.U + CPU_clkdiv := CPU_next + + withClock(CPU_tick.asClock) { + val cpu = Module(new CPU) + cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt) + cpu.io.instruction_valid := rom_loader.io.load_finished + mem.io.instruction_address := cpu.io.instruction_address + cpu.io.instruction := mem.io.instruction + cpu.io.debug_read_address := 0.U + + when(!rom_loader.io.load_finished) { + rom_loader.io.bundle <> mem.io.bundle + cpu.io.memory_bundle.read_data := 0.U + }.otherwise { + rom_loader.io.bundle.read_data := 0.U + when(cpu.io.device_select === 4.U) { + cpu.io.memory_bundle <> timer.io.bundle + }.elsewhen(cpu.io.device_select === 2.U) { // deviceSelect = highest 3 bits of address, thus 0x4000_0000 is mapped to UART + cpu.io.memory_bundle <> uart.io.bundle + }.otherwise { + cpu.io.memory_bundle <> mem.io.bundle + } + } + } + + // LED, blinks every second + val led_count = RegInit(0.U(32.W)) + when (led_count >= clock_freq.U) { + led_count := 0.U + }.otherwise { + led_count := led_count + 1.U + } + io.led := (led_count >= (clock_freq.U >> 1)) + + +} + +object VerilogGenerator extends App { + (new ChiselStage).execute( + Array("-X", "verilog", "-td", "verilog/z710"), + Seq(ChiselGeneratorAnnotation(() => new Top("say_goodbye.asmbin"))) // program to run on CPU + ) +} \ No newline at end of file diff --git a/lab3/src/test/scala/riscv/BoardTest.scala b/lab3/src/test/scala/riscv/BoardTest.scala index 40bd459..cbccc73 100644 --- a/lab3/src/test/scala/riscv/BoardTest.scala +++ b/lab3/src/test/scala/riscv/BoardTest.scala @@ -7,13 +7,13 @@ import chisel3._ import chisel3.util.{is, switch} import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec -import board.z710.Top +import board.{z710, z710v1_3, verilator} -class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { - behavior of "Board simulation" +class Z710_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Z710 Board simulation" it should "say goodbye " in { - test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => + test(new z710.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => for (i <- 1 to 50000) { c.clock.step(5) @@ -23,3 +23,17 @@ class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { } } +class Z710v13_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Z710v1.3 Board simulation" + it should "say goodbye " in { + test(new z710v1_3.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => + + for (i <- 1 to 50000) { + c.clock.step(5) + c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used + } + } + } +} + + diff --git a/lab3/verilog/z710v1.3/clock_control.v b/lab3/verilog/z710v1.3/clock_control.v new file mode 100644 index 0000000..39762e2 --- /dev/null +++ b/lab3/verilog/z710v1.3/clock_control.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/11/29 15:52:55 +// Design Name: +// Module Name: clock_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clock_control( + input clk_in, + input clk_enable, + output clk_out + ); + + + // original clock + assign clk_out = clk_in & clk_enable; + +endmodule diff --git a/lab3/verilog/z710v1.3/top_test.v b/lab3/verilog/z710v1.3/top_test.v new file mode 100644 index 0000000..ea6d7a8 --- /dev/null +++ b/lab3/verilog/z710v1.3/top_test.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/12/01 15:46:54 +// Design Name: +// Module Name: top_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top_test( + + ); + + reg clock; + reg reset; + reg constant_zero = 1'b0; + + wire io_led, io_tx; + + localparam CLK_PERIOD = 10; + initial begin + clock = 1'b0; + forever #( CLK_PERIOD / 2 ) clock = ~clock; + end + + + initial begin + reset = 1; // need a down edge to init all components + #(CLK_PERIOD) reset = 0; // NOTE!!: must happen together with clock down edge! + end + + Top mytop(clock, reset, io_tx, constant_zero, io_led ); + +endmodule diff --git a/lab3/vivado/z710v1.3/README.md b/lab3/vivado/z710v1.3/README.md new file mode 100644 index 0000000..84bed4e --- /dev/null +++ b/lab3/vivado/z710v1.3/README.md @@ -0,0 +1,87 @@ +# 如何使用脚本烧录 CPU 至 Zynq7010 FPGA V1.3_24/02 开发板并从 UART 读取输出 + +## 0. 预先准备 + +在执行下述步骤前，请确保完成： + +1. 通过 CPUTest 确保实现无误. +2. 在 `src\main\scala\z710v1.3\Top.scala` 运行 `VerilogGenerator` 并生成 `verilog\z710v1.3\Top.v` 。 +3. 确认您的板子确实为如下板子，**并调整好下图中 UART 选择的跳线（序号①处）**、连接好右侧的线。 + + +Alt Text + + + +接下来将使用 Vivado 2020 或 2022 版本，更高版本应当也适用。您将在命令行调用这些工具，如果您已经将其所在目录添加到系统变量 PATH 中，则可直接在命令行中输入 `vivado` 进行调用，如目录 `E:\Xilinx\Vivado\2020.1\bin\vivado` 。 +若还没有添加，可以使用 E:\Xilinx\Vivado\2020.1\bin\vivado 来代替。 + +若您使用 2020.1 或较久版本的 Xilinx 工具，在 Windows Powershell 中执行将在额外弹出的窗口中运行 `vivado` 和 `xsct`。您可以在命令前添加 `cmd /c` 以指定其在 cmd 中运行并保留输出至本窗口。 + +**以下操作均默认在 `vivado/z710v1.3` 目录下打开终端并执行，您可以使用 cd 命令切换目录。** + + +## 1. 生成 Vivado 项目 + +执行指令 + +```pwsh +vivado -mode batch -source ./rv-z710v1.3-20.tcl +``` + +这将生成 Vivado 项目，成功后应能看见 `rv-z710v1.3-20\rv-z710v1.3-20.xpr` 文件，注意中途输出有无报错。 + +## 2. 生成比特流文件 + +执行指令 + +```pwsh +vivado -mode batch -source ./generate_bitstream.tcl +``` + +这可能耗费较长时间，成功后，您应看见 `vivado\z710v1.3\rv-z710v1.3-20\rv-z710v1.3-20.runs\impl_1\design_1_wrapper.bit` 文件，或成功的输出信息（可能略有不同）： + +```text +... +Creating bitmap... +Creating bitstream... +Writing bitstream ./design_1_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +128 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2220.910 ; gain = 419.598 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:21 2024... +[Mon Nov 18 17:22:26 2024] impl_1 finished +wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:05 . Memory (MB): peak = 1074.246 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:26 2024... +``` + +## 3. 烧录至开发板 + +确认您的开发板已调整跳线为使用 UART3 接口，见 [预先准备](#0-预先准备)。 + +将您的开发板连接至电脑，包括连接 USB-UART 的 type-C 口线缆 和 JTAG 烧录接口共两个口。若成功连接，您可在设备管理器 - 端口（COM 和 LPT）中看到 `USB Serial Port (COMx)` 端口，其中 `x` 为端口号，后面打开串口时就使用这个 COM 口。 + +然后执行指令 + +```pwsh +vivado -mode batch -source ./program_device.tcl +``` + +若烧录成功，您应看见开发板中央的核心小板亮起绿灯，见 [预先准备](#0-预先准备) 图中的序号④。随后打开 PL_SW1 以开启时钟信号。 + +使用软件打开串口，您可以使用 MobaXTerm、XCom 或 Vitis 等来打开串口，设置 baud rate 为 115200，数据位 8、停止位 1、无校验位，即可收到 CPU 的输出 UART 信息，切换 PL_SW2 以发送 reset 信号重置 CPU 打印。 + + + +## For Maintainers + +Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。 +本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的： + +- reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。 +- `say_goodbye.c` 中打印间隔调大，因为时钟信号只有 50MHz +- 其他引线等资源参考 resources 下的内容 +- 其他可参考 Z710 的 README.md diff --git a/lab3/vivado/z710v1.3/generate_bitstream.tcl b/lab3/vivado/z710v1.3/generate_bitstream.tcl new file mode 100644 index 0000000..bc67b1f --- /dev/null +++ b/lab3/vivado/z710v1.3/generate_bitstream.tcl @@ -0,0 +1,63 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +# setup variables +set project_dir "./rv-z710v1.3-20" +set project_name "rv-z710v1.3-20" + +open_project $project_dir/$project_name.xpr + +update_module_reference design_1_Top_0_0 + +while 1 { + if { [catch {launch_runs synth_1 -jobs 4 } ] } { + regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "17-69"] } { + puts "Out of date, reset runs" + reset_runs synth_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run synth_1 + +while 1 { + if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } { + regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "12-1088"] } { + puts "Out of date, reset runs" + reset_runs impl_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run impl_1 + diff --git a/lab3/vivado/z710v1.3/program_device.tcl b/lab3/vivado/z710v1.3/program_device.tcl new file mode 100644 index 0000000..e1badd3 --- /dev/null +++ b/lab3/vivado/z710v1.3/program_device.tcl @@ -0,0 +1,24 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +open_hw_manager +connect_hw_server -allow_non_jtag +open_hw_target +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +set_property PROGRAM.FILE {./rv-z710v1.3-20/rv-z710v1.3-20.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +close_hw_target diff --git a/lab3/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx b/lab3/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx new file mode 100644 index 0000000..3a190a8 Binary files /dev/null and b/lab3/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx differ diff --git a/lab3/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf b/lab3/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf new file mode 100644 index 0000000..75b2812 Binary files /dev/null and b/lab3/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf differ diff --git a/lab3/vivado/z710v1.3/resources/board-explain.png b/lab3/vivado/z710v1.3/resources/board-explain.png new file mode 100644 index 0000000..32e3577 Binary files /dev/null and b/lab3/vivado/z710v1.3/resources/board-explain.png differ diff --git a/lab3/vivado/z710v1.3/resources/运存DDR3计算.txt b/lab3/vivado/z710v1.3/resources/运存DDR3计算.txt new file mode 100644 index 0000000..f35231a --- /dev/null +++ b/lab3/vivado/z710v1.3/resources/运存DDR3计算.txt @@ -0,0 +1,2 @@ +1. 看有几块运存，本核心板有两块DDR3 +2. DDR的数据手册, DDR3的芯片是 NT5CC256M16EP-EK，一块是4Gb的，两块就是8Gb，即是整个核心板的DDR3为1GB \ No newline at end of file diff --git a/lab3/vivado/z710v1.3/rv-z710v1.3-20.tcl b/lab3/vivado/z710v1.3/rv-z710v1.3-20.tcl new file mode 100644 index 0000000..088a23e --- /dev/null +++ b/lab3/vivado/z710v1.3/rv-z710v1.3-20.tcl @@ -0,0 +1,700 @@ +#***************************************************************************************** +# Vivado (TM) v2020.1 (64-bit) +# +# rv-z710v1.3-20.tcl: Tcl script for re-creating project 'rv-z710v1.3-20' +# +# Generated by Vivado on Mon Nov 18 16:57:58 +0800 2024 +# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (rv-z710v1.3-20.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/Top.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/clock_control.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/z710v1.3.xdc" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "rv-z710v1.3-20" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "rv-z710v1.3-20.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/rv-z710v1.3-20"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../verilog/z710v1.3/Top.v"] \ + [file normalize "${origin_dir}/../../verilog/z710v1.3/clock_control.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +# set files [list \ +# [file normalize "${origin_dir}/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ +# ] +# set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "design_1_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/z710v1.3.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/z710v1.3.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj +set_property -name "top" -value "Top" -objects $obj +set_property -name "top_file" -value "../../verilog/z710v1.3/Top.v" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added +if { [get_files Top.v] == "" } { + import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/Top.v +} +if { [get_files clock_control.v] == "" } { + import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/clock_control.v +} + + +# Proc to create BD design_1 +proc cr_bd_design_1 { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# Top, clock_control + + + + # CHANGE DESIGN NAME HERE + set design_name design_1 + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:util_vector_logic:2.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + Top\ + clock_control\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set UART0_RX_0 [ create_bd_port -dir I -type data UART0_RX_0 ] + set UART0_TX_0 [ create_bd_port -dir O UART0_TX_0 ] + set clk_enable [ create_bd_port -dir I -type ce clk_enable ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_led [ create_bd_port -dir O io_led ] + set io_reset [ create_bd_port -dir I io_reset ] + + # Create instance: Top_0, and set properties + set block_name Top + set block_cell_name Top_0 + if { [catch {set Top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Top_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] [get_bd_pins /Top_0/reset] + + # Create instance: clock_control_0, and set properties + set block_name clock_control + set block_cell_name clock_control_0 + if { [catch {set clock_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $clock_control_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [ list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_notgate.png} \ + ] $util_vector_logic_0 + + # Create port connections + connect_bd_net -net Top_0_io_led [get_bd_ports io_led] [get_bd_pins Top_0/io_led] + connect_bd_net -net Top_0_io_tx [get_bd_ports UART0_TX_0] [get_bd_pins Top_0/io_tx] + connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins Top_0/io_rx] + connect_bd_net -net clk_enable_1 [get_bd_ports clk_enable] [get_bd_pins clock_control_0/clk_enable] + connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out] + connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in] + connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins util_vector_logic_0/Op1] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins Top_0/reset] [get_bd_pins util_vector_logic_0/Res] + + # Create address segments + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-220,-106", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS +# -string -flagsOSRD +preplace port io_clock -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port clk_enable -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD +preplace port UART0_RX_0 -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port UART0_TX_0 -pg 1 -lvl 3 -x 540 -y 170 -defaultsOSRD +preplace port io_led -pg 1 -lvl 3 -x 540 -y 190 -defaultsOSRD +preplace port io_reset -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD +preplace inst Top_0 -pg 1 -lvl 2 -x 420 -y 180 -defaultsOSRD +preplace inst clock_control_0 -pg 1 -lvl 1 -x 170 -y 70 -defaultsOSRD +preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 170 -y 180 -defaultsOSRD +preplace netloc io_clock_1 1 0 1 NJ 60 +preplace netloc clock_control_0_clk_out 1 1 1 320 70n +preplace netloc UART0_RX_0_1 1 0 2 NJ 240 320J +preplace netloc Top_0_io_tx 1 2 1 NJ 170 +preplace netloc clk_enable_1 1 0 1 NJ 80 +preplace netloc Top_0_io_led 1 2 1 NJ 190 +preplace netloc io_reset_1 1 0 1 NJ 180 +preplace netloc util_vector_logic_0_Res 1 1 1 NJ 180 +levelinfo -pg 1 0 170 420 540 +pagesize -pg 1 -db -bbox -sgen -140 0 680 260 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_design_1() +cr_bd_design_1 "" +set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] + +# make wrapper for design_1.db +set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] +add_files -norecurse -fileset sources_1 $wrapper_path + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2020" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2020" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/lab3/vivado/z710v1.3/z710v1.3.xdc b/lab3/vivado/z710v1.3/z710v1.3.xdc new file mode 100644 index 0000000..816425d --- /dev/null +++ b/lab3/vivado/z710v1.3/z710v1.3.xdc @@ -0,0 +1,31 @@ +## This file is for SYSU computer organization courses. +## used for Zynq7010 fpga revision 1.3 2024/02 + + + +# clock, 50 MHz +set_property IOSTANDARD LVCMOS33 [get_ports io_clock]; +set_property PACKAGE_PIN U18 [get_ports io_clock]; +create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock]; + +# LEDs +set_property IOSTANDARD LVCMOS33 [get_ports io_led]; +set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0 +#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1]; +#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2]; + +# switches +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enable]; # PL_SW1 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_SW2 + +# do NOT assign reset to ANY BUTTON in Vivado 2020, its Utility Vector Logic Not cause unstable TX output +# while this isn't present in Vivado 2022 + + + +# UART ports +# rxd assigned to constant 1 +set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0] +set_property PACKAGE_PIN J15 [get_ports UART0_TX_0] +set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0] +set_property PACKAGE_PIN T19 [get_ports UART0_RX_0] diff --git a/lab4/src/test/scala/riscv/BoardTest.scala b/lab4/src/test/scala/riscv/BoardTest.scala index 40bd459..cbccc73 100644 --- a/lab4/src/test/scala/riscv/BoardTest.scala +++ b/lab4/src/test/scala/riscv/BoardTest.scala @@ -7,13 +7,13 @@ import chisel3._ import chisel3.util.{is, switch} import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec -import board.z710.Top +import board.{z710, z710v1_3, verilator} -class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { - behavior of "Board simulation" +class Z710_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Z710 Board simulation" it should "say goodbye " in { - test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => + test(new z710.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => for (i <- 1 to 50000) { c.clock.step(5) @@ -23,3 +23,17 @@ class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { } } +class Z710v13_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Z710v1.3 Board simulation" + it should "say goodbye " in { + test(new z710v1_3.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => + + for (i <- 1 to 50000) { + c.clock.step(5) + c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used + } + } + } +} + + diff --git a/lab4/verilog/z710v1.3/clock_control.v b/lab4/verilog/z710v1.3/clock_control.v new file mode 100644 index 0000000..39762e2 --- /dev/null +++ b/lab4/verilog/z710v1.3/clock_control.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/11/29 15:52:55 +// Design Name: +// Module Name: clock_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clock_control( + input clk_in, + input clk_enable, + output clk_out + ); + + + // original clock + assign clk_out = clk_in & clk_enable; + +endmodule diff --git a/lab4/verilog/z710v1.3/top_test.v b/lab4/verilog/z710v1.3/top_test.v new file mode 100644 index 0000000..ea6d7a8 --- /dev/null +++ b/lab4/verilog/z710v1.3/top_test.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/12/01 15:46:54 +// Design Name: +// Module Name: top_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top_test( + + ); + + reg clock; + reg reset; + reg constant_zero = 1'b0; + + wire io_led, io_tx; + + localparam CLK_PERIOD = 10; + initial begin + clock = 1'b0; + forever #( CLK_PERIOD / 2 ) clock = ~clock; + end + + + initial begin + reset = 1; // need a down edge to init all components + #(CLK_PERIOD) reset = 0; // NOTE!!: must happen together with clock down edge! + end + + Top mytop(clock, reset, io_tx, constant_zero, io_led ); + +endmodule diff --git a/lab4/vivado/z710v1.3/README.md b/lab4/vivado/z710v1.3/README.md new file mode 100644 index 0000000..84bed4e --- /dev/null +++ b/lab4/vivado/z710v1.3/README.md @@ -0,0 +1,87 @@ +# 如何使用脚本烧录 CPU 至 Zynq7010 FPGA V1.3_24/02 开发板并从 UART 读取输出 + +## 0. 预先准备 + +在执行下述步骤前，请确保完成： + +1. 通过 CPUTest 确保实现无误. +2. 在 `src\main\scala\z710v1.3\Top.scala` 运行 `VerilogGenerator` 并生成 `verilog\z710v1.3\Top.v` 。 +3. 确认您的板子确实为如下板子，**并调整好下图中 UART 选择的跳线（序号①处）**、连接好右侧的线。 + + +Alt Text + + + +接下来将使用 Vivado 2020 或 2022 版本，更高版本应当也适用。您将在命令行调用这些工具，如果您已经将其所在目录添加到系统变量 PATH 中，则可直接在命令行中输入 `vivado` 进行调用，如目录 `E:\Xilinx\Vivado\2020.1\bin\vivado` 。 +若还没有添加，可以使用 E:\Xilinx\Vivado\2020.1\bin\vivado 来代替。 + +若您使用 2020.1 或较久版本的 Xilinx 工具，在 Windows Powershell 中执行将在额外弹出的窗口中运行 `vivado` 和 `xsct`。您可以在命令前添加 `cmd /c` 以指定其在 cmd 中运行并保留输出至本窗口。 + +**以下操作均默认在 `vivado/z710v1.3` 目录下打开终端并执行，您可以使用 cd 命令切换目录。** + + +## 1. 生成 Vivado 项目 + +执行指令 + +```pwsh +vivado -mode batch -source ./rv-z710v1.3-20.tcl +``` + +这将生成 Vivado 项目，成功后应能看见 `rv-z710v1.3-20\rv-z710v1.3-20.xpr` 文件，注意中途输出有无报错。 + +## 2. 生成比特流文件 + +执行指令 + +```pwsh +vivado -mode batch -source ./generate_bitstream.tcl +``` + +这可能耗费较长时间，成功后，您应看见 `vivado\z710v1.3\rv-z710v1.3-20\rv-z710v1.3-20.runs\impl_1\design_1_wrapper.bit` 文件，或成功的输出信息（可能略有不同）： + +```text +... +Creating bitmap... +Creating bitstream... +Writing bitstream ./design_1_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +128 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2220.910 ; gain = 419.598 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:21 2024... +[Mon Nov 18 17:22:26 2024] impl_1 finished +wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:05 . Memory (MB): peak = 1074.246 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:26 2024... +``` + +## 3. 烧录至开发板 + +确认您的开发板已调整跳线为使用 UART3 接口，见 [预先准备](#0-预先准备)。 + +将您的开发板连接至电脑，包括连接 USB-UART 的 type-C 口线缆 和 JTAG 烧录接口共两个口。若成功连接，您可在设备管理器 - 端口（COM 和 LPT）中看到 `USB Serial Port (COMx)` 端口，其中 `x` 为端口号，后面打开串口时就使用这个 COM 口。 + +然后执行指令 + +```pwsh +vivado -mode batch -source ./program_device.tcl +``` + +若烧录成功，您应看见开发板中央的核心小板亮起绿灯，见 [预先准备](#0-预先准备) 图中的序号④。随后打开 PL_SW1 以开启时钟信号。 + +使用软件打开串口，您可以使用 MobaXTerm、XCom 或 Vitis 等来打开串口，设置 baud rate 为 115200，数据位 8、停止位 1、无校验位，即可收到 CPU 的输出 UART 信息，切换 PL_SW2 以发送 reset 信号重置 CPU 打印。 + + + +## For Maintainers + +Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。 +本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的： + +- reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。 +- `say_goodbye.c` 中打印间隔调大，因为时钟信号只有 50MHz +- 其他引线等资源参考 resources 下的内容 +- 其他可参考 Z710 的 README.md diff --git a/lab4/vivado/z710v1.3/generate_bitstream.tcl b/lab4/vivado/z710v1.3/generate_bitstream.tcl new file mode 100644 index 0000000..bc67b1f --- /dev/null +++ b/lab4/vivado/z710v1.3/generate_bitstream.tcl @@ -0,0 +1,63 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +# setup variables +set project_dir "./rv-z710v1.3-20" +set project_name "rv-z710v1.3-20" + +open_project $project_dir/$project_name.xpr + +update_module_reference design_1_Top_0_0 + +while 1 { + if { [catch {launch_runs synth_1 -jobs 4 } ] } { + regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "17-69"] } { + puts "Out of date, reset runs" + reset_runs synth_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run synth_1 + +while 1 { + if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } { + regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "12-1088"] } { + puts "Out of date, reset runs" + reset_runs impl_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run impl_1 + diff --git a/lab4/vivado/z710v1.3/program_device.tcl b/lab4/vivado/z710v1.3/program_device.tcl new file mode 100644 index 0000000..e1badd3 --- /dev/null +++ b/lab4/vivado/z710v1.3/program_device.tcl @@ -0,0 +1,24 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +open_hw_manager +connect_hw_server -allow_non_jtag +open_hw_target +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +set_property PROGRAM.FILE {./rv-z710v1.3-20/rv-z710v1.3-20.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +close_hw_target diff --git a/lab4/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx b/lab4/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx new file mode 100644 index 0000000..3a190a8 Binary files /dev/null and b/lab4/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx differ diff --git a/lab4/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf b/lab4/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf new file mode 100644 index 0000000..75b2812 Binary files /dev/null and b/lab4/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf differ diff --git a/lab4/vivado/z710v1.3/resources/board-explain.png b/lab4/vivado/z710v1.3/resources/board-explain.png new file mode 100644 index 0000000..32e3577 Binary files /dev/null and b/lab4/vivado/z710v1.3/resources/board-explain.png differ diff --git a/lab4/vivado/z710v1.3/resources/运存DDR3计算.txt b/lab4/vivado/z710v1.3/resources/运存DDR3计算.txt new file mode 100644 index 0000000..f35231a --- /dev/null +++ b/lab4/vivado/z710v1.3/resources/运存DDR3计算.txt @@ -0,0 +1,2 @@ +1. 看有几块运存，本核心板有两块DDR3 +2. DDR的数据手册, DDR3的芯片是 NT5CC256M16EP-EK，一块是4Gb的，两块就是8Gb，即是整个核心板的DDR3为1GB \ No newline at end of file diff --git a/lab4/vivado/z710v1.3/rv-z710v1.3-20.tcl b/lab4/vivado/z710v1.3/rv-z710v1.3-20.tcl new file mode 100644 index 0000000..088a23e --- /dev/null +++ b/lab4/vivado/z710v1.3/rv-z710v1.3-20.tcl @@ -0,0 +1,700 @@ +#***************************************************************************************** +# Vivado (TM) v2020.1 (64-bit) +# +# rv-z710v1.3-20.tcl: Tcl script for re-creating project 'rv-z710v1.3-20' +# +# Generated by Vivado on Mon Nov 18 16:57:58 +0800 2024 +# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (rv-z710v1.3-20.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/Top.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/clock_control.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/z710v1.3.xdc" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "rv-z710v1.3-20" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "rv-z710v1.3-20.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/rv-z710v1.3-20"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../verilog/z710v1.3/Top.v"] \ + [file normalize "${origin_dir}/../../verilog/z710v1.3/clock_control.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +# set files [list \ +# [file normalize "${origin_dir}/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ +# ] +# set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "design_1_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/z710v1.3.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/z710v1.3.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj +set_property -name "top" -value "Top" -objects $obj +set_property -name "top_file" -value "../../verilog/z710v1.3/Top.v" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added +if { [get_files Top.v] == "" } { + import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/Top.v +} +if { [get_files clock_control.v] == "" } { + import_files -quiet -fileset sources_1 ../../verilog/z710v1.3/clock_control.v +} + + +# Proc to create BD design_1 +proc cr_bd_design_1 { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# Top, clock_control + + + + # CHANGE DESIGN NAME HERE + set design_name design_1 + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:util_vector_logic:2.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + Top\ + clock_control\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set UART0_RX_0 [ create_bd_port -dir I -type data UART0_RX_0 ] + set UART0_TX_0 [ create_bd_port -dir O UART0_TX_0 ] + set clk_enable [ create_bd_port -dir I -type ce clk_enable ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_led [ create_bd_port -dir O io_led ] + set io_reset [ create_bd_port -dir I io_reset ] + + # Create instance: Top_0, and set properties + set block_name Top + set block_cell_name Top_0 + if { [catch {set Top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Top_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] [get_bd_pins /Top_0/reset] + + # Create instance: clock_control_0, and set properties + set block_name clock_control + set block_cell_name clock_control_0 + if { [catch {set clock_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $clock_control_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [ list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_notgate.png} \ + ] $util_vector_logic_0 + + # Create port connections + connect_bd_net -net Top_0_io_led [get_bd_ports io_led] [get_bd_pins Top_0/io_led] + connect_bd_net -net Top_0_io_tx [get_bd_ports UART0_TX_0] [get_bd_pins Top_0/io_tx] + connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins Top_0/io_rx] + connect_bd_net -net clk_enable_1 [get_bd_ports clk_enable] [get_bd_pins clock_control_0/clk_enable] + connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out] + connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in] + connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins util_vector_logic_0/Op1] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins Top_0/reset] [get_bd_pins util_vector_logic_0/Res] + + # Create address segments + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-220,-106", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS +# -string -flagsOSRD +preplace port io_clock -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port clk_enable -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD +preplace port UART0_RX_0 -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port UART0_TX_0 -pg 1 -lvl 3 -x 540 -y 170 -defaultsOSRD +preplace port io_led -pg 1 -lvl 3 -x 540 -y 190 -defaultsOSRD +preplace port io_reset -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD +preplace inst Top_0 -pg 1 -lvl 2 -x 420 -y 180 -defaultsOSRD +preplace inst clock_control_0 -pg 1 -lvl 1 -x 170 -y 70 -defaultsOSRD +preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 170 -y 180 -defaultsOSRD +preplace netloc io_clock_1 1 0 1 NJ 60 +preplace netloc clock_control_0_clk_out 1 1 1 320 70n +preplace netloc UART0_RX_0_1 1 0 2 NJ 240 320J +preplace netloc Top_0_io_tx 1 2 1 NJ 170 +preplace netloc clk_enable_1 1 0 1 NJ 80 +preplace netloc Top_0_io_led 1 2 1 NJ 190 +preplace netloc io_reset_1 1 0 1 NJ 180 +preplace netloc util_vector_logic_0_Res 1 1 1 NJ 180 +levelinfo -pg 1 0 170 420 540 +pagesize -pg 1 -db -bbox -sgen -140 0 680 260 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_design_1() +cr_bd_design_1 "" +set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] + +# make wrapper for design_1.db +set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] +add_files -norecurse -fileset sources_1 $wrapper_path + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2020" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2020" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/lab4/vivado/z710v1.3/z710v1.3.xdc b/lab4/vivado/z710v1.3/z710v1.3.xdc new file mode 100644 index 0000000..816425d --- /dev/null +++ b/lab4/vivado/z710v1.3/z710v1.3.xdc @@ -0,0 +1,31 @@ +## This file is for SYSU computer organization courses. +## used for Zynq7010 fpga revision 1.3 2024/02 + + + +# clock, 50 MHz +set_property IOSTANDARD LVCMOS33 [get_ports io_clock]; +set_property PACKAGE_PIN U18 [get_ports io_clock]; +create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock]; + +# LEDs +set_property IOSTANDARD LVCMOS33 [get_ports io_led]; +set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0 +#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1]; +#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2]; + +# switches +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enable]; # PL_SW1 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_SW2 + +# do NOT assign reset to ANY BUTTON in Vivado 2020, its Utility Vector Logic Not cause unstable TX output +# while this isn't present in Vivado 2022 + + + +# UART ports +# rxd assigned to constant 1 +set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0] +set_property PACKAGE_PIN J15 [get_ports UART0_TX_0] +set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0] +set_property PACKAGE_PIN T19 [get_ports UART0_RX_0]