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updated vidado-vitis uart workflow scripts

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Generated Top.v can be burnt to Z7-10 board with these scripts with Vivado 2020.1, versions above should be OK.

- vivado project now generates with just a single script
- vitis project now runs with a single script
This commit is contained in:
PurplePower
2023-12-25 17:10:17 +08:00
parent bcd11625a6
commit 85c4621957
12 changed files with 1363 additions and 1028 deletions
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10
lab1/vivado/z710/generate_bitstream.tcl
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@@ -12,7 +12,7 @@
# See the License for the specific language governing permissions and
# limitations under the License.
source open_project.tcl
source open_project-v2020.tcl
while 1 {
if { [catch {launch_runs synth_1 -jobs 4 } ] } {
@@ -54,8 +54,8 @@ while 1 {
wait_on_run impl_1
# copy the bitstream so vivado GUI still finds it
file copy riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit
# this will export platform .xsz
write_hw_platform -fixed -include_bit -force -file ./riscv-z710/Top.xsa
# export hardware platform to Vitis
set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]
write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa