diff --git a/lab4/.gitignore b/lab4/.gitignore
index 946816b..cc5fac1 100644
--- a/lab4/.gitignore
+++ b/lab4/.gitignore
@@ -354,5 +354,6 @@ verilog/verilator/*
 vivado/basys3/riscv-basys3
 vivado/pynq/riscv-pynq
 vivado/pynq/NA
+vivado/z710/riscv-z710
 .vscode
 .metals
diff --git a/lab4/src/main/scala/bus/AXI4Lite.scala b/lab4/src/main/scala/bus/AXI4Lite.scala
index 212419a..274fafa 100644
--- a/lab4/src/main/scala/bus/AXI4Lite.scala
+++ b/lab4/src/main/scala/bus/AXI4Lite.scala
@@ -153,7 +153,62 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module {
   val BRESP = WireInit(0.U(AXI4Lite.respWidth))
   io.channels.write_response_channel.BRESP := BRESP
   //lab4(BUS)
-
+  switch(state) {
+    is(AXI4LiteStates.Idle) {
+      read := false.B
+      write := false.B
+      RVALID := false.B
+      BVALID := false.B
+      when(io.channels.write_address_channel.AWVALID) {
+        state := AXI4LiteStates.WriteAddr
+      }.elsewhen(io.channels.read_address_channel.ARVALID) {
+        state := AXI4LiteStates.ReadAddr
+      }
+    }
+    is(AXI4LiteStates.ReadAddr) {
+      ARREADY := true.B
+      when(io.channels.read_address_channel.ARVALID && ARREADY) {
+        state := AXI4LiteStates.ReadData
+        addr := io.channels.read_address_channel.ARADDR
+        read := true.B
+        ARREADY := false.B
+      }
+    }
+    is(AXI4LiteStates.ReadData) {
+      RVALID := io.bundle.read_valid
+      when(io.channels.read_data_channel.RREADY && RVALID) {
+        state := AXI4LiteStates.Idle
+        RVALID := false.B
+      }
+    }
+    is(AXI4LiteStates.WriteAddr) {
+      AWREADY := true.B
+      when(io.channels.write_address_channel.AWVALID && AWREADY) {
+        addr := io.channels.write_address_channel.AWADDR
+        state := AXI4LiteStates.WriteData
+        AWREADY := false.B
+      }
+    }
+    is(AXI4LiteStates.WriteData) {
+      WREADY := true.B
+      when(io.channels.write_data_channel.WVALID && WREADY) {
+        state := AXI4LiteStates.WriteResp
+        write_data := io.channels.write_data_channel.WDATA
+        write_strobe := io.channels.write_data_channel.WSTRB.asBools
+        write := true.B
+        WREADY := false.B
+      }
+    }
+    is(AXI4LiteStates.WriteResp) {
+      WREADY := false.B
+      BVALID := true.B
+      when(io.channels.write_response_channel.BREADY && BVALID) {
+        state := AXI4LiteStates.Idle
+        write := false.B
+        BVALID := false.B
+      }
+    }
+  }
 }
 
 class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
@@ -191,7 +246,67 @@ class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
   io.channels.write_data_channel.WSTRB := write_strobe.asUInt
   val BREADY = RegInit(false.B)
   io.channels.write_response_channel.BREADY := BREADY
-
   //lab4(BUS)
-
+  switch(state) {
+    is(AXI4LiteStates.Idle) {
+      WVALID := false.B
+      AWVALID := false.B
+      ARVALID := false.B
+      RREADY := false.B
+      read_valid := false.B
+      write_valid := false.B
+      when(io.bundle.write) {
+        state := AXI4LiteStates.WriteAddr
+        addr := io.bundle.address
+        write_data := io.bundle.write_data
+        write_strobe := io.bundle.write_strobe
+      }.elsewhen(io.bundle.read) {
+        state := AXI4LiteStates.ReadAddr
+        addr := io.bundle.address
+      }
+    }
+    is(AXI4LiteStates.ReadAddr) {
+      ARVALID := true.B
+      io.channels.read_address_channel.ARADDR := addr
+      when(io.channels.read_address_channel.ARREADY && ARVALID) {
+        state := AXI4LiteStates.ReadData
+        io.channels.read_address_channel.ARADDR := addr
+        ARVALID := false.B
+      }
+    }
+    is(AXI4LiteStates.ReadData) {
+      when(io.channels.read_data_channel.RVALID && io.channels.read_data_channel.RRESP === 0.U) {
+        state := AXI4LiteStates.Idle
+        read_valid := true.B
+        RREADY := true.B
+        read_data := io.channels.read_data_channel.RDATA
+      }
+    }
+    is(AXI4LiteStates.WriteAddr) {
+      AWVALID := true.B
+      io.channels.write_address_channel.AWADDR := addr
+      when(io.channels.write_address_channel.AWREADY && AWVALID) {
+        state := AXI4LiteStates.WriteData
+        io.channels.write_address_channel.AWADDR := addr
+        AWVALID := false.B
+      }
+    }
+    is(AXI4LiteStates.WriteData) {
+      WVALID := true.B
+      io.channels.write_address_channel.AWADDR := addr
+      when(io.channels.write_data_channel.WREADY && WVALID) {
+        io.channels.write_address_channel.AWADDR := addr
+        state := AXI4LiteStates.WriteResp
+        WVALID := false.B
+      }
+    }
+    is(AXI4LiteStates.WriteResp) {
+      BREADY := true.B
+      when(io.channels.write_response_channel.BVALID && BREADY) {
+        state := AXI4LiteStates.Idle
+        write_valid := true.B
+        BREADY := false.B
+      }
+    }
+  }
 }
diff --git a/lab4/verilog/z710/Top_reset.v b/lab4/verilog/z710/Top_reset.v
new file mode 100644
index 0000000..4349e47
--- /dev/null
+++ b/lab4/verilog/z710/Top_reset.v
@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 16:32:40
+// Design Name: 
+// Module Name: Top_reset
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Top_reset(
+    input reset
+    );
+    initial begin
+        reset = 1;
+        #25 reset = 0;
+    end
+    
+    
+endmodule
diff --git a/lab4/verilog/z710/clock_control.v b/lab4/verilog/z710/clock_control.v
new file mode 100644
index 0000000..f4e882d
--- /dev/null
+++ b/lab4/verilog/z710/clock_control.v
@@ -0,0 +1,29 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 15:52:55
+// Design Name: 
+// Module Name: clock_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clock_control(
+    input clk_in,
+    input enable_clk,
+    output clk_out
+    );
+    assign clk_out = clk_in & enable_clk;
+endmodule
diff --git a/lab4/verilog/z710/design_1.bd b/lab4/verilog/z710/design_1.bd
new file mode 100644
index 0000000..39f979a
--- /dev/null
+++ b/lab4/verilog/z710/design_1.bd
@@ -0,0 +1,459 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0xD2682A7282870375",
+      "device": "xc7z010clg400-1",
+      "name": "design_1",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2020.1",
+      "validated": "true"
+    },
+    "design_tree": {
+      "processing_system7_0": "",
+      "clock_control_0": "",
+      "xlconstant_0": "",
+      "Top_0": ""
+    },
+    "interface_ports": {
+      "DDR": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
+        "parameters": {
+          "CAN_DEBUG": {
+            "value": "false",
+            "value_src": "default"
+          },
+          "TIMEPERIOD_PS": {
+            "value": "1250",
+            "value_src": "default"
+          },
+          "MEMORY_TYPE": {
+            "value": "COMPONENTS",
+            "value_src": "default"
+          },
+          "DATA_WIDTH": {
+            "value": "8",
+            "value_src": "default"
+          },
+          "CS_ENABLED": {
+            "value": "true",
+            "value_src": "default"
+          },
+          "DATA_MASK_ENABLED": {
+            "value": "true",
+            "value_src": "default"
+          },
+          "SLOT": {
+            "value": "Single",
+            "value_src": "default"
+          },
+          "MEM_ADDR_MAP": {
+            "value": "ROW_COLUMN_BANK",
+            "value_src": "default"
+          },
+          "BURST_LENGTH": {
+            "value": "8",
+            "value_src": "default"
+          },
+          "AXI_ARBITRATION_SCHEME": {
+            "value": "TDM",
+            "value_src": "default"
+          },
+          "CAS_LATENCY": {
+            "value": "11",
+            "value_src": "default"
+          },
+          "CAS_WRITE_LATENCY": {
+            "value": "11",
+            "value_src": "default"
+          }
+        }
+      },
+      "FIXED_IO": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
+        "parameters": {
+          "CAN_DEBUG": {
+            "value": "false",
+            "value_src": "default"
+          }
+        }
+      }
+    },
+    "ports": {
+      "io_clock": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "design_1_clock",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "100000000"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.000",
+            "value_src": "default"
+          }
+        }
+      },
+      "io_alive_led": {
+        "direction": "O"
+      },
+      "io_reset": {
+        "direction": "I",
+        "parameters": {
+          "POLARITY": {
+            "value": "",
+            "value_src": "weak"
+          }
+        }
+      },
+      "enable_clk": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "design_1_enable_clk_0",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "100000000",
+            "value_src": "default"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.000",
+            "value_src": "default"
+          }
+        }
+      }
+    },
+    "components": {
+      "processing_system7_0": {
+        "vlnv": "xilinx.com:ip:processing_system7:5.5",
+        "xci_name": "design_1_processing_system7_0_0",
+        "parameters": {
+          "PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
+            "value": "666.666687"
+          },
+          "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
+            "value": "10.158730"
+          },
+          "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
+            "value": "50.000000"
+          },
+          "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
+            "value": "200.000000"
+          },
+          "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
+            "value": "10.000000"
+          },
+          "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
+            "value": "200.000000"
+          },
+          "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
+            "value": "100.000000"
+          },
+          "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
+            "value": "111.111115"
+          },
+          "PCW_CLK0_FREQ": {
+            "value": "50000000"
+          },
+          "PCW_CLK1_FREQ": {
+            "value": "10000000"
+          },
+          "PCW_CLK2_FREQ": {
+            "value": "10000000"
+          },
+          "PCW_CLK3_FREQ": {
+            "value": "10000000"
+          },
+          "PCW_DDR_RAM_HIGHADDR": {
+            "value": "0x1FFFFFFF"
+          },
+          "PCW_EN_EMIO_UART0": {
+            "value": "1"
+          },
+          "PCW_EN_UART0": {
+            "value": "1"
+          },
+          "PCW_EN_UART1": {
+            "value": "1"
+          },
+          "PCW_FPGA_FCLK0_ENABLE": {
+            "value": "1"
+          },
+          "PCW_MIO_48_IOTYPE": {
+            "value": "LVCMOS 3.3V"
+          },
+          "PCW_MIO_48_PULLUP": {
+            "value": "enabled"
+          },
+          "PCW_MIO_48_SLEW": {
+            "value": "slow"
+          },
+          "PCW_MIO_49_IOTYPE": {
+            "value": "LVCMOS 3.3V"
+          },
+          "PCW_MIO_49_PULLUP": {
+            "value": "enabled"
+          },
+          "PCW_MIO_49_SLEW": {
+            "value": "slow"
+          },
+          "PCW_MIO_TREE_PERIPHERALS": {
+            "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
+          },
+          "PCW_MIO_TREE_SIGNALS": {
+            "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
+          },
+          "PCW_UART0_GRP_FULL_ENABLE": {
+            "value": "0"
+          },
+          "PCW_UART0_PERIPHERAL_ENABLE": {
+            "value": "1"
+          },
+          "PCW_UART0_UART0_IO": {
+            "value": "EMIO"
+          },
+          "PCW_UART1_GRP_FULL_ENABLE": {
+            "value": "0"
+          },
+          "PCW_UART1_PERIPHERAL_ENABLE": {
+            "value": "1"
+          },
+          "PCW_UART1_UART1_IO": {
+            "value": "MIO 48 .. 49"
+          },
+          "PCW_UART_PERIPHERAL_FREQMHZ": {
+            "value": "100"
+          },
+          "PCW_UART_PERIPHERAL_VALID": {
+            "value": "1"
+          },
+          "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
+            "value": "533.333374"
+          },
+          "PCW_USE_M_AXI_GP0": {
+            "value": "0"
+          }
+        }
+      },
+      "clock_control_0": {
+        "vlnv": "xilinx.com:module_ref:clock_control:1.0",
+        "xci_name": "design_1_clock_control_0_0",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "clock_control",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "clk_in": {
+            "direction": "I",
+            "parameters": {
+              "CLK_DOMAIN": {
+                "value": "design_1_clock",
+                "value_src": "default_prop"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "user_prop"
+              },
+              "PHASE": {
+                "value": "0.000",
+                "value_src": "default_prop"
+              }
+            }
+          },
+          "enable_clk": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "CLK_DOMAIN": {
+                "value": "design_1_enable_clk_0",
+                "value_src": "default_prop"
+              }
+            }
+          },
+          "clk_out": {
+            "direction": "O",
+            "parameters": {
+              "CLK_DOMAIN": {
+                "value": "",
+                "value_src": "weak"
+              },
+              "FREQ_HZ": {
+                "value": "",
+                "value_src": "weak"
+              },
+              "PHASE": {
+                "value": "",
+                "value_src": "weak"
+              }
+            }
+          }
+        }
+      },
+      "xlconstant_0": {
+        "vlnv": "xilinx.com:ip:xlconstant:1.1",
+        "xci_name": "design_1_xlconstant_0_0"
+      },
+      "Top_0": {
+        "vlnv": "xilinx.com:module_ref:Top:1.0",
+        "xci_name": "design_1_Top_0_0",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "Top",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "clock": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "ASSOCIATED_RESET": {
+                "value": "reset",
+                "value_src": "constant"
+              }
+            }
+          },
+          "reset": {
+            "type": "rst",
+            "direction": "I"
+          },
+          "io_led": {
+            "direction": "O"
+          },
+          "io_tx": {
+            "direction": "O"
+          },
+          "io_rx": {
+            "direction": "I"
+          }
+        }
+      }
+    },
+    "interface_nets": {
+      "processing_system7_0_DDR": {
+        "interface_ports": [
+          "DDR",
+          "processing_system7_0/DDR"
+        ]
+      },
+      "processing_system7_0_FIXED_IO": {
+        "interface_ports": [
+          "FIXED_IO",
+          "processing_system7_0/FIXED_IO"
+        ]
+      }
+    },
+    "nets": {
+      "Top_0_io_tx": {
+        "ports": [
+          "Top_0/io_tx",
+          "processing_system7_0/UART0_RX"
+        ]
+      },
+      "Top_0_io_led": {
+        "ports": [
+          "Top_0/io_led",
+          "io_alive_led"
+        ]
+      },
+      "io_reset_1": {
+        "ports": [
+          "io_reset",
+          "Top_0/reset"
+        ]
+      },
+      "io_clock_1": {
+        "ports": [
+          "io_clock",
+          "clock_control_0/clk_in"
+        ]
+      },
+      "enable_clk_0_1": {
+        "ports": [
+          "enable_clk",
+          "clock_control_0/enable_clk"
+        ]
+      },
+      "clock_control_0_clk_out": {
+        "ports": [
+          "clock_control_0/clk_out",
+          "Top_0/clock"
+        ]
+      },
+      "xlconstant_0_dout": {
+        "ports": [
+          "xlconstant_0/dout",
+          "Top_0/io_rx"
+        ]
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/lab4/verilog/z710/design_1_wrapper.v b/lab4/verilog/z710/design_1_wrapper.v
new file mode 100644
index 0000000..e148ca7
--- /dev/null
+++ b/lab4/verilog/z710/design_1_wrapper.v
@@ -0,0 +1,116 @@
+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
+//Date        : Sun Dec 10 14:11:15 2023
+//Host        : Tokisakix running 64-bit major release  (build 9200)
+//Command     : generate_target design_1_wrapper.bd
+//Design      : design_1_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb,
+    enable_clk,
+    io_alive_led,
+    io_clock,
+    io_reset);
+  inout [14:0]DDR_addr;
+  inout [2:0]DDR_ba;
+  inout DDR_cas_n;
+  inout DDR_ck_n;
+  inout DDR_ck_p;
+  inout DDR_cke;
+  inout DDR_cs_n;
+  inout [3:0]DDR_dm;
+  inout [31:0]DDR_dq;
+  inout [3:0]DDR_dqs_n;
+  inout [3:0]DDR_dqs_p;
+  inout DDR_odt;
+  inout DDR_ras_n;
+  inout DDR_reset_n;
+  inout DDR_we_n;
+  inout FIXED_IO_ddr_vrn;
+  inout FIXED_IO_ddr_vrp;
+  inout [53:0]FIXED_IO_mio;
+  inout FIXED_IO_ps_clk;
+  inout FIXED_IO_ps_porb;
+  inout FIXED_IO_ps_srstb;
+  input enable_clk;
+  output io_alive_led;
+  input io_clock;
+  input io_reset;
+
+  wire [14:0]DDR_addr;
+  wire [2:0]DDR_ba;
+  wire DDR_cas_n;
+  wire DDR_ck_n;
+  wire DDR_ck_p;
+  wire DDR_cke;
+  wire DDR_cs_n;
+  wire [3:0]DDR_dm;
+  wire [31:0]DDR_dq;
+  wire [3:0]DDR_dqs_n;
+  wire [3:0]DDR_dqs_p;
+  wire DDR_odt;
+  wire DDR_ras_n;
+  wire DDR_reset_n;
+  wire DDR_we_n;
+  wire FIXED_IO_ddr_vrn;
+  wire FIXED_IO_ddr_vrp;
+  wire [53:0]FIXED_IO_mio;
+  wire FIXED_IO_ps_clk;
+  wire FIXED_IO_ps_porb;
+  wire FIXED_IO_ps_srstb;
+  wire enable_clk;
+  wire io_alive_led;
+  wire io_clock;
+  wire io_reset;
+
+  design_1 design_1_i
+       (.DDR_addr(DDR_addr),
+        .DDR_ba(DDR_ba),
+        .DDR_cas_n(DDR_cas_n),
+        .DDR_ck_n(DDR_ck_n),
+        .DDR_ck_p(DDR_ck_p),
+        .DDR_cke(DDR_cke),
+        .DDR_cs_n(DDR_cs_n),
+        .DDR_dm(DDR_dm),
+        .DDR_dq(DDR_dq),
+        .DDR_dqs_n(DDR_dqs_n),
+        .DDR_dqs_p(DDR_dqs_p),
+        .DDR_odt(DDR_odt),
+        .DDR_ras_n(DDR_ras_n),
+        .DDR_reset_n(DDR_reset_n),
+        .DDR_we_n(DDR_we_n),
+        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
+        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
+        .FIXED_IO_mio(FIXED_IO_mio),
+        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
+        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
+        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
+        .enable_clk(enable_clk),
+        .io_alive_led(io_alive_led),
+        .io_clock(io_clock),
+        .io_reset(io_reset));
+endmodule
diff --git a/lab4/verilog/z710/pass_through.v b/lab4/verilog/z710/pass_through.v
new file mode 100644
index 0000000..daf212e
--- /dev/null
+++ b/lab4/verilog/z710/pass_through.v
@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 16:38:00
+// Design Name: 
+// Module Name: pass_through
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pass_through(
+    input in,
+    output out
+    );
+    assign out = in;
+endmodule
diff --git a/lab4/verilog/z710/test.v b/lab4/verilog/z710/test.v
new file mode 100644
index 0000000..b250a66
--- /dev/null
+++ b/lab4/verilog/z710/test.v
@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/12/17 16:31:05
+// Design Name: 
+// Module Name: test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module test();
+reg clock;
+reg reset;
+initial begin
+clock = 0;
+forever #1 clock = ~clock;
+end
+initial begin
+reset = 1;
+#2 reset = 0;
+end
+Top top(clock, reset);
+endmodule
\ No newline at end of file
diff --git a/lab4/verilog/z710/top_test.v b/lab4/verilog/z710/top_test.v
new file mode 100644
index 0000000..a2398e8
--- /dev/null
+++ b/lab4/verilog/z710/top_test.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 15:46:54
+// Design Name: 
+// Module Name: top_test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_test(
+
+    );
+    
+    reg clock;
+    reg reset;
+    reg constant_zero = 1'b0;
+    
+    wire io_led, io_tx;
+    
+    localparam CLK_PERIOD = 20;
+    initial begin
+        clock = 1'b0;
+        forever #( CLK_PERIOD / 2 ) clock = ~clock;
+    end
+    
+    
+    initial begin
+        reset = 1;  // need a down edge to init all components
+        #21  reset = 0;  // NOTE!!: must happen together with clock down edge!
+    end
+    
+    Top mytop(clock, reset, io_led, io_tx, constant_zero);
+    
+endmodule
diff --git a/lab4/verilog/z710/uart_control.v b/lab4/verilog/z710/uart_control.v
new file mode 100644
index 0000000..a73b6d2
--- /dev/null
+++ b/lab4/verilog/z710/uart_control.v
@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/30 00:51:08
+// Design Name: 
+// Module Name: uart_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module uart_control(
+    input enable_uart,
+    input tx_in,
+    output tx_out
+    );
+    assign tx_out = (enable_uart) ? tx_in : 1'h1;
+
+endmodule
diff --git a/lab4/vivado/z710/generate_and_program.tcl b/lab4/vivado/z710/generate_and_program.tcl
new file mode 100644
index 0000000..71df1af
--- /dev/null
+++ b/lab4/vivado/z710/generate_and_program.tcl
@@ -0,0 +1,17 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+source generate_bitstream.tcl
+source program_device.tcl
\ No newline at end of file
diff --git a/lab4/vivado/z710/generate_bitstream.tcl b/lab4/vivado/z710/generate_bitstream.tcl
new file mode 100644
index 0000000..0a025be
--- /dev/null
+++ b/lab4/vivado/z710/generate_bitstream.tcl
@@ -0,0 +1,57 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source open_project.tcl
+
+while 1 {
+    if { [catch {launch_runs synth_1 -jobs 4 } ] } {
+        regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
+        if { [string equal $code "12-978"] } {
+            puts "Already generated and up-to-date"
+            break
+        } elseif { [string equal $code "17-69"] } {
+            puts "Out of date, reset runs"
+            reset_runs synth_1
+            continue
+        } else {
+            puts "UNKNOWN ERROR!!! $errorInfo"
+            exit
+        }
+    }
+    break
+}
+
+wait_on_run synth_1
+
+while 1 {
+    if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
+        regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
+        if { [string equal $code "12-978"] } {
+            puts "Already generated and up-to-date"
+            break
+        } elseif { [string equal $code "12-1088"] } {
+            puts "Out of date, reset runs"
+            reset_runs impl_1
+            continue
+        } else {
+            puts "UNKNOWN ERROR!!! $errorInfo"
+            exit
+        }
+    }
+    break
+}
+
+wait_on_run impl_1
+
+file rename riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit
\ No newline at end of file
diff --git a/lab4/vivado/z710/helloworld.c b/lab4/vivado/z710/helloworld.c
new file mode 100644
index 0000000..1f04639
--- /dev/null
+++ b/lab4/vivado/z710/helloworld.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE   BAUD RATE                        |
+ * ------------------------------------------------
+ *   uartns550   9600
+ *   uartlite    Configurable only in HW design
+ *   ps7_uart    115200 (configured by bootrom/bsp)
+ */
+
+#include <stdio.h>
+#include "platform.h"
+#include "xil_printf.h"
+//#include "xuartps_hw.h"	// already include in xuartps.h
+#include "xuartps.h"
+#include "xparameters.h"
+
+XUartPs uart_ps;	//  instance of the UART device
+
+
+
+
+int main()
+{
+    init_platform();
+    xil_printf("\nHello World\n\r");
+
+
+    // test on UART ps
+    int BUFFER_SIZE = 16;	// do not set too much to overflow FIFO
+    char send_buffer[BUFFER_SIZE + 1];
+    char recv_buffer[BUFFER_SIZE + 1];
+    int status = 0;
+    XUartPs_Config *config;
+
+
+    for (int i = 0; i < BUFFER_SIZE; i++) send_buffer[i] = i % 256;
+
+    config = XUartPs_LookupConfig(XPAR_XUARTPS_0_BASEADDR);	// CHANGE UART PORT HERE!!!
+    if (config == NULL) {
+    	printf("Error in config lookup!\n");
+    	return XST_FAILURE;
+    }
+
+
+    status = XUartPs_CfgInitialize(&uart_ps, config, config->BaseAddress);
+    if (status != XST_SUCCESS) {
+    	printf("Error in cfg initialize!\n");
+		return XST_FAILURE;
+    }
+	XUartPs_SetBaudRate(&uart_ps, 115200);
+
+    /* Check hardware build. */
+	status = XUartPs_SelfTest(&uart_ps);
+	if (status != XST_SUCCESS) {
+		printf("Error in self test!\n");
+		return XST_FAILURE;
+	}
+
+
+	/* Configure UART mode */
+	int mode = XUartPs_ReadReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET);
+	printf("original mode = 0x%x\n", mode);
+	XUartPs_WriteReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET,
+			(XUARTPS_MR_STOPMODE_2_BIT | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT));
+
+
+
+    XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
+
+
+
+
+    int recv_cnt = 0;
+    while (1) {
+    	int recved = XUartPs_Recv(&uart_ps, (u8*)(recv_buffer + 0), BUFFER_SIZE);
+    	recv_cnt += recved;
+    	recv_buffer[recv_cnt] = 0;	// end
+    	if (recv_cnt >= 1) {
+//    		printf("%s", recv_buffer);
+//    		printf("%i\n", recv_buffer[0]);
+
+    		/* print string manually */
+    		for (int j = 0; j < BUFFER_SIZE; j++) {
+    			if (recv_buffer[j] != 0) {
+    				printf("%c", recv_buffer[j]);
+    			} else {
+    				break;
+    			}
+    		}
+
+    		recv_cnt = 0;
+    	}
+    }
+
+    /* Restore to normal mode. */
+	XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
+
+
+    cleanup_platform();
+    return 0;
+}
diff --git a/lab4/vivado/z710/open_project.tcl b/lab4/vivado/z710/open_project.tcl
new file mode 100644
index 0000000..f758198
--- /dev/null
+++ b/lab4/vivado/z710/open_project.tcl
@@ -0,0 +1,33 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+
+# set variables
+set project_dir riscv-z710
+set project_name riscv-z710
+set part xc7z010clg400-1
+set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v}
+set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v}
+
+# open the project. will create one if it doesn't exist 
+if {[file exist $project_dir]} {
+    # check that it's a directory
+    if {! [file isdirectory $project_dir]} {
+        puts "$project_dir exists, but it's a file"
+    }
+    open_project $project_dir/$project_name.xpr -part $part 
+} else {
+    source riscv-z710.tcl
+}
\ No newline at end of file
diff --git a/lab4/vivado/z710/program_device.tcl b/lab4/vivado/z710/program_device.tcl
new file mode 100644
index 0000000..dc784fe
--- /dev/null
+++ b/lab4/vivado/z710/program_device.tcl
@@ -0,0 +1,24 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Only tested on Vivado 2020.1 on Windows 10
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_server [current_hw_server]
+open_hw_target [lindex [get_hw_targets] 0]
+set_property PROGRAM.FILE {./riscv-z710/riscv-z710.runs/impl_1/Top.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+close_hw_target
diff --git a/lab4/vivado/z710/riscv-z710.tcl b/lab4/vivado/z710/riscv-z710.tcl
new file mode 100644
index 0000000..4c115d1
--- /dev/null
+++ b/lab4/vivado/z710/riscv-z710.tcl
@@ -0,0 +1,1267 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.1 (64-bit)
+#
+# riscv-z710.tcl: Tcl script for re-creating project 'riscv-z710'
+#
+# Generated by Vivado on Sun Dec 10 23:14:15 +0800 2023
+# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (riscv-z710.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "C:/Users/21168/Desktop/yatcpu/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/design_1.bd"
+#    "C:/Users/21168/Desktop/yatcpu/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/clock_control.v"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/Top.v"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/Top_reset.v"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/pass_through.v"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/uart_control.v"
+#    "C:/Users/21168/Desktop/yatcpu/vivado/z710/z710.xdc"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/test.v"
+#    "C:/Users/21168/Desktop/yatcpu/verilog/z710/top_test.v"
+#
+#*****************************************************************************************
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "riscv-z710"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "riscv-z710.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/riscv-z710"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710/Top.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710/Top_reset.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710/pass_through.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710/uart_control.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/../../verilog/z710/design_1.bd" ]\
+ [file normalize "${origin_dir}/../../verilog/z710/design_1_wrapper.v" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file [file normalize "${origin_dir}/../../verilog/z710/design_1.bd" ]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list $file]]
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "design_1_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'design_1_Top_0_0' fileset (if not found)
+if {[string equal [get_filesets -quiet design_1_Top_0_0] ""]} {
+  create_fileset -blockset design_1_Top_0_0
+}
+
+# Set 'design_1_Top_0_0' fileset object
+set obj [get_filesets design_1_Top_0_0]
+# Empty (no sources present)
+
+# Set 'design_1_Top_0_0' fileset properties
+set obj [get_filesets design_1_Top_0_0]
+set_property -name "top" -value "design_1_Top_0_0" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'design_1_processing_system7_0_0' fileset (if not found)
+if {[string equal [get_filesets -quiet design_1_processing_system7_0_0] ""]} {
+  create_fileset -blockset design_1_processing_system7_0_0
+}
+
+# Set 'design_1_processing_system7_0_0' fileset object
+set obj [get_filesets design_1_processing_system7_0_0]
+# Empty (no sources present)
+
+# Set 'design_1_processing_system7_0_0' fileset properties
+set obj [get_filesets design_1_processing_system7_0_0]
+set_property -name "top" -value "design_1_processing_system7_0_0" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'design_1_clock_control_0_0' fileset (if not found)
+if {[string equal [get_filesets -quiet design_1_clock_control_0_0] ""]} {
+  create_fileset -blockset design_1_clock_control_0_0
+}
+
+# Set 'design_1_clock_control_0_0' fileset object
+set obj [get_filesets design_1_clock_control_0_0]
+# Empty (no sources present)
+
+# Set 'design_1_clock_control_0_0' fileset properties
+set obj [get_filesets design_1_clock_control_0_0]
+set_property -name "top" -value "design_1_clock_control_0_0" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/z710.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/z710.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/../../verilog/z710/test.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710/top_test.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+# None
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "design_1_wrapper" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# Create 'design_1_Top_0_0_synth_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_Top_0_0_synth_1] ""]} {
+    create_run -name design_1_Top_0_0_synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset design_1_Top_0_0
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs design_1_Top_0_0_synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs design_1_Top_0_0_synth_1]
+}
+set obj [get_runs design_1_Top_0_0_synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_Top_0_0_synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_synth_1] design_1_Top_0_0_synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs design_1_Top_0_0_synth_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_synth_1] design_1_Top_0_0_synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs design_1_Top_0_0_synth_1]
+set_property -name "constrset" -value "design_1_Top_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# Create 'design_1_processing_system7_0_0_synth_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_processing_system7_0_0_synth_1] ""]} {
+    create_run -name design_1_processing_system7_0_0_synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset design_1_processing_system7_0_0
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs design_1_processing_system7_0_0_synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs design_1_processing_system7_0_0_synth_1]
+}
+set obj [get_runs design_1_processing_system7_0_0_synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_processing_system7_0_0_synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_synth_1] design_1_processing_system7_0_0_synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs design_1_processing_system7_0_0_synth_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_synth_1] design_1_processing_system7_0_0_synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs design_1_processing_system7_0_0_synth_1]
+set_property -name "constrset" -value "design_1_processing_system7_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# Create 'design_1_clock_control_0_0_synth_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_clock_control_0_0_synth_1] ""]} {
+    create_run -name design_1_clock_control_0_0_synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset design_1_clock_control_0_0
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs design_1_clock_control_0_0_synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs design_1_clock_control_0_0_synth_1]
+}
+set obj [get_runs design_1_clock_control_0_0_synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_clock_control_0_0_synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_synth_1] design_1_clock_control_0_0_synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs design_1_clock_control_0_0_synth_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_synth_1] design_1_clock_control_0_0_synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs design_1_clock_control_0_0_synth_1]
+set_property -name "constrset" -value "design_1_clock_control_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# Create 'design_1_Top_0_0_impl_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_Top_0_0_impl_1] ""]} {
+    create_run -name design_1_Top_0_0_impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset design_1_Top_0_0 -parent_run design_1_Top_0_0_synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs design_1_Top_0_0_impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs design_1_Top_0_0_impl_1]
+}
+set obj [get_runs design_1_Top_0_0_impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_Top_0_0_impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_Top_0_0_impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_Top_0_0_impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_Top_0_0_impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs design_1_Top_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_Top_0_0_impl_1] design_1_Top_0_0_impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs design_1_Top_0_0_impl_1]
+set_property -name "constrset" -value "design_1_Top_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "include_in_archive" -value "0" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# Create 'design_1_processing_system7_0_0_impl_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_processing_system7_0_0_impl_1] ""]} {
+    create_run -name design_1_processing_system7_0_0_impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset design_1_processing_system7_0_0 -parent_run design_1_processing_system7_0_0_synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs design_1_processing_system7_0_0_impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs design_1_processing_system7_0_0_impl_1]
+}
+set obj [get_runs design_1_processing_system7_0_0_impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_processing_system7_0_0_impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs design_1_processing_system7_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_processing_system7_0_0_impl_1] design_1_processing_system7_0_0_impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs design_1_processing_system7_0_0_impl_1]
+set_property -name "constrset" -value "design_1_processing_system7_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "include_in_archive" -value "0" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# Create 'design_1_clock_control_0_0_impl_1' run (if not found)
+if {[string equal [get_runs -quiet design_1_clock_control_0_0_impl_1] ""]} {
+    create_run -name design_1_clock_control_0_0_impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset design_1_clock_control_0_0 -parent_run design_1_clock_control_0_0_synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs design_1_clock_control_0_0_impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs design_1_clock_control_0_0_impl_1]
+}
+set obj [get_runs design_1_clock_control_0_0_impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'design_1_clock_control_0_0_impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs design_1_clock_control_0_0_impl_1
+}
+set obj [get_report_configs -of_objects [get_runs design_1_clock_control_0_0_impl_1] design_1_clock_control_0_0_impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs design_1_clock_control_0_0_impl_1]
+set_property -name "constrset" -value "design_1_clock_control_0_0" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "include_in_archive" -value "0" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
diff --git a/lab4/vivado/z710/run_simulation.tcl b/lab4/vivado/z710/run_simulation.tcl
new file mode 100644
index 0000000..7c1a23c
--- /dev/null
+++ b/lab4/vivado/z710/run_simulation.tcl
@@ -0,0 +1,24 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source open_project.tcl
+
+launch_simulation
+restart
+open_vcd
+log_wave -recursive [get_object /test/top/cpu/*]
+log_vcd [get_object /test/top/cpu/*]
+run 1000ns
+close_vcd
+close_sim
diff --git a/lab4/vivado/z710/z710.xdc b/lab4/vivado/z710/z710.xdc
new file mode 100644
index 0000000..c6e297d
--- /dev/null
+++ b/lab4/vivado/z710/z710.xdc
@@ -0,0 +1,216 @@
+## This file is a general .xdc for the Zybo Z7 Rev. B
+## It is compatible with the Zybo Z7-20 and Zybo Z7-10
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+
+#set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
+#set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
+
+##Clock signal
+set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports io_clock]
+create_clock -period 20.000 -name sys_clk_pin -waveform {0.000 10.000} -add [get_ports io_clock]
+
+
+
+
+# UART 1
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS18 } [get_ports { io_tx }];
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { reset }]; # bind to BTN1
+#set_property IOSTANDARD LVCMOS18 [get_ports { io_tx }];
+#set_property IOSTANDARD LVCMOS33 [get_ports { reset }];
+
+
+
+
+##Switches
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports enable_clk]
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports enable_uart]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
+
+
+##Buttons
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports io_reset]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L24N_T3_34 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn_tri_io[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn_tri_io[3] }]; #IO_L7P_T1_34 Sch=btn[3]
+
+
+##LEDs
+set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_alive_led]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
+
+
+##RGB LED 5 (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
+#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
+#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
+
+##RGB LED 6
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
+
+
+##Audio Codec
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
+
+
+##USB-OTG over-current detect pin
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
+
+
+##Fan (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
+
+
+##HDMI RX
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
+
+##HDMI RX CEC (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
+
+
+##HDMI TX
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
+
+##HDMI TX CEC
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33     } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVCMOS33     } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33     } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33     } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33     } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33     } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V6    IOSTANDARD LVCMOS33     } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33     } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33     } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
+
+
+##Pcam MIPI CSI-2 Connector
+## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
+#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
+#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 	PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
+
+
+##Unloaded Crypto Chip SWI (for future use)
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
+
+
+##Unconnected Pins (Zybo Z7-20 only)
+#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
+#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
+#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
+#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
+#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
+#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
+#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
+#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
+#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
+#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
+#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
+#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
+
+
+
+