zzh/2025-yatcpu
1
0
Fork 0
mirror of https://github.com/handsomezhuzhu/2025-yatcpu.git synced 2026-02-20 20:10:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update Top.scala

Browse Source
This commit is contained in:
PurplePower
2024-01-24 15:11:56 +08:00
parent b9294c0bd1
commit 55aff2d301
1 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lab1/src/main/scala/board/z710/Top.scala
View File

@@ -31,14 +31,14 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
val mem = Module(new Memory(Parameters.MemorySizeInWords))
// val hdmi_display = Module(new HDMIDisplay)
// val display = Module(new CharacterDisplay)
val timer = Module(new Timer)
// val timer = Module(new Timer)
val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
val dummy = Module(new Dummy)
// display.io.bundle <> dummy.io.bundle
mem.io.bundle <> dummy.io.bundle
mem.io.debug_read_address := 0.U
timer.io.bundle <> dummy.io.bundle
// timer.io.bundle <> dummy.io.bundle
uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd
uart.io.rxd := io.rx
@@ -60,9 +60,9 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
withClock(CPU_tick.asClock) {
val cpu = Module(new CPU)
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
cpu.io.csr_regs_debug_read_address := 0.U
cpu.io.regs_debug_read_address := 0.U
// cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
// cpu.io.csr_regs_debug_read_address := 0.U
// cpu.io.regs_debug_read_address := 0.U
cpu.io.debug_read_address := 0.U
// cpu.io.memory_bundle.read_data := 0.U
cpu.io.instruction_valid := rom_loader.io.load_finished