updates Z7-10 for lab3 and lab4

lab3/src/main/scala/board/z710/Top.scala

@@ -28,11 +28,15 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
 
     val led = Output(Bool())  // z710 has few LEDs, use one for running indicator
   })
+
+  // original ref clock is 125MHz, divided in clock_control.v by 5 to avoid total negative slack too large
+  val clock_freq = 25_000_000 
+
   val mem = Module(new Memory(Parameters.MemorySizeInWords))
   // val hdmi_display = Module(new HDMIDisplay)
   // val display = Module(new CharacterDisplay)
   val timer = Module(new Timer)
-  val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
+  val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error
   val dummy = Module(new Dummy)
 
   // display.io.bundle <> dummy.io.bundle
@@ -81,14 +85,13 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
   }
 
   // LED, blinks every second
-  val clock_freq = 40_000_000.U
   val led_count = RegInit(0.U(32.W))
-  when (led_count >= clock_freq) {
+  when (led_count >= clock_freq.U) {
     led_count := 0.U
   }.otherwise {
     led_count := led_count + 1.U
   }
-  io.led := (led_count >= (clock_freq >> 1))
+  io.led := (led_count >= (clock_freq.U >> 1))
 
 
 }

lab3/verilog/z710/clock_control.v

@@ -1,46 +1,25 @@
 `timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 2023/11/29 15:52:55
-// Design Name: 
-// Module Name: clock_control
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
+// fpga4student.com: FPGA projects, VHDL projects, Verilog projects
+// Verilog project: Verilog code for clock divider on FPGA
+// Top level Verilog code for clock divider on FPGA
 module clock_control(
-    input clk_in,
+    input clock_in,
     input enable_clk,
-    output clk_out
-    );
-    
-    // if clock is divided
-    localparam clk_div = 2; // clock is diveded by half of divisor
-    reg [3:0] cnt = 4'd0;
-    reg out = 1'b0;
-    always @(posedge clk_in) begin 
-        cnt <= cnt + 4'd1;
-        if (cnt >= (clk_div - 1)) begin
-            out <= ~out;
-            cnt <= 0;
+    output reg clock_out
+);
+    reg[3:0] counter = 4'd0;
+    parameter DIVISOR = 4'd5;
+    // The frequency of the output clk_out
+    //  = The frequency of the input clk_in divided by DIVISOR
+    // For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
+    // You will modify the DIVISOR parameter value to 28'd50.000.000
+    // Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
+    always @(posedge clock_in)
+    begin
+        counter <= counter + 4'd1;
+        if(counter>=(DIVISOR-1)) begin
+            counter <= 4'd0;
         end
+        clock_out <= ((counter<DIVISOR/2)?1'b1:1'b0) && enable_clk;
     end
-    assign clk_out = out & enable_clk;
-    
-    
-    // original clock
-//    assign clk_out = clk_in & enable_clk;
-    
 endmodule

lab4/src/main/scala/board/z710/Top.scala

@@ -94,7 +94,7 @@ class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
 
 
   
-  val clock_freq = 100_000_000.U
+  val clock_freq = 125_000_000.U
 
   val led_count = RegInit(0.U(32.W))
   when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M