lab4差MemoryTestF

lab4/src/main/scala/bus/AXI4Lite.scala

@@ -134,6 +134,7 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module {
   val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B)))
   io.bundle.write_strobe := write_strobe
 
+  val read_issued = RegInit(false.B)
   val ARREADY = RegInit(false.B)
   io.channels.read_address_channel.ARREADY := ARREADY
   val RVALID = RegInit(false.B)
@@ -153,7 +154,95 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module {
   val BRESP = WireInit(0.U(AXI4Lite.respWidth))
   io.channels.write_response_channel.BRESP := BRESP
   //lab4(BUS)
-  
+  switch(state) {
+    is(AXI4LiteStates.Idle) {
+      // 默认状态：所有控制信号为低
+      ARREADY := false.B
+      RVALID := false.B
+      AWREADY := false.B
+      WREADY := false.B
+      BVALID := false.B
+
+      // 检测读地址通道的请求
+      when(io.channels.read_address_channel.ARVALID) {
+        read := false.B  // 清除之前的read
+        state := AXI4LiteStates.ReadAddr
+        addr := io.channels.read_address_channel.ARADDR
+        ARREADY := true.B
+      }.elsewhen(io.channels.write_address_channel.AWVALID) {
+        write := false.B  // 清除之前的write
+        // 检测写地址通道的请求
+        state := AXI4LiteStates.WriteAddr
+        addr := io.channels.write_address_channel.AWADDR
+        AWREADY := true.B
+      }.otherwise {
+        // 没有新请求时，延迟清除read/write信号
+        read := false.B
+        write := false.B
+      }
+    }
+
+    is(AXI4LiteStates.ReadAddr) {
+      // 读地址握手完成，发起读请求并进入ReadData
+      ARREADY := false.B
+      read := true.B
+      read_issued := false.B
+      state := AXI4LiteStates.ReadData
+    }
+
+    is(AXI4LiteStates.ReadData) {
+      // 保持read信号有效
+      read := true.B
+
+      when(!read_issued) {
+        // 第一个周期：等待Memory准备数据
+        read_issued := true.B
+      }.otherwise {
+        // 第二个周期及之后：检查数据是否准备好
+        when(!RVALID && io.bundle.read_valid) {
+          // 数据准备好，置RVALID
+          RVALID := true.B
+        }.elsewhen(RVALID && io.channels.read_data_channel.RREADY) {
+          // 握手完成，返回Idle（read会在Idle状态延迟清除）
+          RVALID := false.B
+          read_issued := false.B
+          state := AXI4LiteStates.Idle
+        }
+      }
+    }
+
+    is(AXI4LiteStates.WriteAddr) {
+      // 写地址握手完成，等待写数据
+      AWREADY := false.B
+      when(io.channels.write_data_channel.WVALID) {
+        // 收到写数据
+        state := AXI4LiteStates.WriteData
+        for (i <- 0 until Parameters.WordSize) {
+          write_strobe(i) := io.channels.write_data_channel.WSTRB(i)
+        }
+        WREADY := true.B
+        write := true.B
+      }
+    }
+
+    is(AXI4LiteStates.WriteData) {
+      // 写数据握手完成，等待写入完成后发送响应
+      WREADY := false.B
+      write := false.B
+      state := AXI4LiteStates.WriteResp
+      BVALID := true.B
+    }
+
+    is(AXI4LiteStates.WriteResp) {
+      // 等待写响应握手
+      when(io.channels.write_response_channel.BREADY) {
+        // 写响应握手完成
+        BVALID := false.B
+        state := AXI4LiteStates.Idle
+      }
+    }
+  }
+
 }
 
 class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
@@ -180,7 +269,7 @@ class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
   val RREADY = RegInit(false.B)
   io.channels.read_data_channel.RREADY := RREADY
 
-  io.bundle.read_data := io.channels.read_data_channel.RDATA
+  io.bundle.read_data := read_data
   val AWVALID = RegInit(false.B)
   io.channels.write_address_channel.AWADDR := 0.U
   io.channels.write_address_channel.AWVALID := AWVALID
@@ -192,5 +281,95 @@ class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
   val BREADY = RegInit(false.B)
   io.channels.write_response_channel.BREADY := BREADY
   //lab4(BUS)
-  
+  // 清零valid信号（如果不是刚刚被置1）
+  when(read_valid) {
+    read_valid := false.B
+  }
+  when(write_valid) {
+    write_valid := false.B
+  }
+
+  switch(state) {
+    is(AXI4LiteStates.Idle) {
+      // 默认状态：所有控制信号为低
+      ARVALID := false.B
+      RREADY := false.B
+      AWVALID := false.B
+      WVALID := false.B
+      BREADY := false.B
+
+      // 检测读请求
+      when(io.bundle.read) {
+        state := AXI4LiteStates.ReadAddr
+        addr := io.bundle.address
+        ARVALID := true.B
+      }.elsewhen(io.bundle.write) {
+        // 检测写请求
+        state := AXI4LiteStates.WriteAddr
+        addr := io.bundle.address
+        write_data := io.bundle.write_data
+        write_strobe := io.bundle.write_strobe
+        AWVALID := true.B
+      }
+    }
+
+    is(AXI4LiteStates.ReadAddr) {
+      // 发送读地址，等待从机响应
+      ARVALID := true.B
+      io.channels.read_address_channel.ARADDR := addr
+      when(io.channels.read_address_channel.ARREADY) {
+        // 读地址握手完成
+        ARVALID := false.B
+        state := AXI4LiteStates.ReadData
+        RREADY := true.B
+      }
+    }
+
+    is(AXI4LiteStates.ReadData) {
+      // 等待读数据，保持RREADY为高
+      RREADY := true.B
+      when(io.channels.read_data_channel.RVALID) {
+        // 读数据握手完成
+        read_data := io.channels.read_data_channel.RDATA
+        RREADY := false.B
+        read_valid := true.B
+        state := AXI4LiteStates.Idle
+      }
+    }
+
+    is(AXI4LiteStates.WriteAddr) {
+      // 发送写地址，等待从机响应
+      AWVALID := true.B
+      io.channels.write_address_channel.AWADDR := addr
+      when(io.channels.write_address_channel.AWREADY) {
+        // 写地址握手完成
+        AWVALID := false.B
+        state := AXI4LiteStates.WriteData
+        WVALID := true.B
+      }
+    }
+
+    is(AXI4LiteStates.WriteData) {
+      // 发送写数据，保持WVALID为高
+      WVALID := true.B
+      when(io.channels.write_data_channel.WREADY) {
+        // 写数据握手完成
+        WVALID := false.B
+        state := AXI4LiteStates.WriteResp
+        BREADY := true.B
+      }
+    }
+
+    is(AXI4LiteStates.WriteResp) {
+      // 等待写响应，保持BREADY为高
+      BREADY := true.B
+      when(io.channels.write_response_channel.BVALID) {
+        // 写响应握手完成
+        BREADY := false.B
+        write_valid := true.B
+        state := AXI4LiteStates.Idle
+      }
+    }
+  }
+
 }