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lab2/朱梓涵24325356/scala/riscv/core/InstructionDecode.scala
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208
lab2/朱梓涵24325356/scala/riscv/core/InstructionDecode.scala
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// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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object InstructionTypes {
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val L = "b0000011".U
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val I = "b0010011".U
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val S = "b0100011".U
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val RM = "b0110011".U
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val B = "b1100011".U
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}
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object Instructions {
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val lui = "b0110111".U
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val nop = "b0000001".U
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val jal = "b1101111".U
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val jalr = "b1100111".U
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val auipc = "b0010111".U
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val csr = "b1110011".U
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val fence = "b0001111".U
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}
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object InstructionsTypeL {
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val lb = "b000".U
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val lh = "b001".U
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val lw = "b010".U
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val lbu = "b100".U
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val lhu = "b101".U
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}
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object InstructionsTypeI {
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val addi = 0.U
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val slli = 1.U
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val slti = 2.U
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val sltiu = 3.U
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val xori = 4.U
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val sri = 5.U
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val ori = 6.U
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val andi = 7.U
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}
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object InstructionsTypeS {
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val sb = "b000".U
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val sh = "b001".U
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val sw = "b010".U
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}
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object InstructionsTypeR {
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val add_sub = 0.U
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val sll = 1.U
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val slt = 2.U
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val sltu = 3.U
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val xor = 4.U
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val sr = 5.U
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val or = 6.U
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val and = 7.U
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}
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object InstructionsTypeM {
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val mul = 0.U
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val mulh = 1.U
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val mulhsu = 2.U
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val mulhum = 3.U
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val div = 4.U
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val divu = 5.U
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val rem = 6.U
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val remu = 7.U
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}
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object InstructionsTypeB {
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val beq = "b000".U
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val bne = "b001".U
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val blt = "b100".U
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val bge = "b101".U
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val bltu = "b110".U
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val bgeu = "b111".U
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}
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object InstructionsTypeCSR {
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val csrrw = "b001".U
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val csrrs = "b010".U
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val csrrc = "b011".U
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val csrrwi = "b101".U
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val csrrsi = "b110".U
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val csrrci = "b111".U
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}
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object InstructionsNop {
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val nop = 0x00000013L.U(Parameters.DataWidth)
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}
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object InstructionsRet {
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val mret = 0x30200073L.U(Parameters.DataWidth)
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val ret = 0x00008067L.U(Parameters.DataWidth)
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}
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object InstructionsEnv {
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val ecall = 0x00000073L.U(Parameters.DataWidth)
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val ebreak = 0x00100073L.U(Parameters.DataWidth)
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}
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object ALUOp1Source {
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val Register = 0.U(1.W)
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val InstructionAddress = 1.U(1.W)
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}
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object ALUOp2Source {
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val Register = 0.U(1.W)
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val Immediate = 1.U(1.W)
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}
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object RegWriteSource {
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val ALUResult = 0.U(2.W)
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val Memory = 1.U(2.W)
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val CSR = 2.U(2.W)
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val NextInstructionAddress = 3.U(2.W)
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}
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class InstructionDecode extends Module {
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val io = IO(new Bundle {
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val instruction = Input(UInt(Parameters.InstructionWidth))
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val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
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val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
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val ex_immediate = Output(UInt(Parameters.DataWidth))
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val ex_aluop1_source = Output(UInt(1.W))
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val ex_aluop2_source = Output(UInt(1.W))
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val memory_read_enable = Output(Bool())
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val memory_write_enable = Output(Bool())
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val wb_reg_write_source = Output(UInt(2.W))
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val reg_write_enable = Output(Bool())
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val reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
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val csr_reg_write_enable = Output(Bool())
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val csr_reg_address = Output(UInt(Parameters.DataWidth))
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})
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val opcode = io.instruction(6, 0)
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val funct3 = io.instruction(14, 12)
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val funct7 = io.instruction(31, 25)
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val rd = io.instruction(11, 7)
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val rs1 = io.instruction(19, 15)
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val rs2 = io.instruction(24, 20)
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io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
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io.regs_reg2_read_address := rs2
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val immediate = MuxLookup(
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opcode,
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Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
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IndexedSeq(
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InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
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InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
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Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
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InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
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InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
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Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
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Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
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Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
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)
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)
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io.ex_immediate := immediate
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io.ex_aluop1_source := Mux(
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opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
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ALUOp1Source.InstructionAddress,
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ALUOp1Source.Register
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)
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io.ex_aluop2_source := Mux(
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opcode === InstructionTypes.RM,
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ALUOp2Source.Register,
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ALUOp2Source.Immediate
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)
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io.memory_read_enable := opcode === InstructionTypes.L
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io.memory_write_enable := opcode === InstructionTypes.S
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io.wb_reg_write_source := MuxLookup(
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opcode,
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RegWriteSource.ALUResult,
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IndexedSeq(
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InstructionTypes.L -> RegWriteSource.Memory,
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Instructions.jal -> RegWriteSource.NextInstructionAddress,
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Instructions.jalr -> RegWriteSource.NextInstructionAddress,
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Instructions.csr -> RegWriteSource.CSR
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)
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)
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io.reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
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(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
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(opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr)
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io.reg_write_address := io.instruction(11, 7)
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io.csr_reg_address := io.instruction(31,20)
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io.csr_reg_write_enable := (opcode === Instructions.csr) && (
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funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi ||
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funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi ||
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funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci
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)
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}
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