lab2打包

lab2/朱梓涵24325356/core/Timer.scala

@@ -0,0 +1,61 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import chisel3.util._
+import riscv.Parameters
+
+class Timer extends Module {
+  val io = IO(new Bundle {
+    val bundle = new RAMBundle
+    val signal_interrupt = Output(Bool())
+
+    val debug_limit = Output(UInt(Parameters.DataWidth))
+    val debug_enabled = Output(Bool())
+  })
+
+
+  val count = RegInit(0.U(32.W))
+  val limit = RegInit(100000000.U(32.W))
+  io.debug_limit := limit
+  val enabled = RegInit(true.B)
+  io.debug_enabled := enabled
+
+  //lab2(CLINTCSR)
+  val address = io.bundle.address
+  io.bundle.read_data := 0.U
+  when(address === 0x4.U) {
+    io.bundle.read_data := limit
+  }.elsewhen(address === 0x8.U) {
+    io.bundle.read_data := enabled
+  }
+
+  when(io.bundle.write_enable) {
+    when(address === 0x4.U) {
+      limit := io.bundle.write_data
+    }.elsewhen(address === 0x8.U) {
+      enabled := io.bundle.write_data(0)
+    }
+  }
+
+  when(enabled && count >= limit) {
+    io.signal_interrupt := true.B
+    count := 0.U
+  }.otherwise {
+    io.signal_interrupt := false.B
+    count := count + 1.U
+  }
+}