diff --git a/lab2/build.sbt b/lab2/build.sbt index 75f138e..e60e1f1 100644 --- a/lab2/build.sbt +++ b/lab2/build.sbt @@ -22,3 +22,6 @@ lazy val root = (project in file(".")) ), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full), ) + + + diff --git a/lab2/实验报告/report.aux b/lab2/实验报告/report.aux new file mode 100644 index 0000000..042175e --- /dev/null +++ b/lab2/实验报告/report.aux @@ -0,0 +1,30 @@ +\relax +\providecommand\hyper@newdestlabel[2]{} +\providecommand*\HyPL@Entry[1]{} +\HyPL@Entry{0<>} +\@writefile{toc}{\contentsline {section}{\numberline {1}实验目的}{1}{section.1}\protected@file@percent } +\@writefile{toc}{\contentsline {section}{\numberline {2}实验环境}{1}{section.2}\protected@file@percent } +\@writefile{toc}{\contentsline {section}{\numberline {3}模块实现与分析}{1}{section.3}\protected@file@percent } +\@writefile{toc}{\contentsline {subsection}{\numberline {3.1}CSR 模块}{2}{subsection.3.1}\protected@file@percent } +\@writefile{toc}{\contentsline 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differ diff --git a/lab2/实验报告/report.tex b/lab2/实验报告/report.tex new file mode 100644 index 0000000..b544b32 --- /dev/null +++ b/lab2/实验报告/report.tex @@ -0,0 +1,280 @@ +\documentclass[12pt]{ctexart} +\usepackage[utf8]{inputenc} +\usepackage[margin=2.5cm]{geometry} +\usepackage{graphicx} +\usepackage{amsmath} +\usepackage{listings} +\usepackage{xcolor} +\usepackage{hyperref} +\hypersetup{ + colorlinks=true, + linkcolor=black, + citecolor=green, + urlcolor=blue, + filecolor=magenta, + pdftitle={实验二：RISC-V CPU 中断处理机制设计与实现}, + pdfauthor={朱梓涵}, + pdfsubject={RISC-V CPU 设计与实现报告}, + pdfkeywords={RISC-V, CPU, Chisel, 中断, CLINT, CSR, 实验报告} +} +\usepackage{fancyhdr} +\usepackage{enumitem} + +% --- 页眉页脚设置 --- +\setlength{\headheight}{15pt} +\pagestyle{fancy} +\fancyhf{} +\fancyhead[L]{\MakeUppercase{实验二：RISC-V CPU 中断处理机制设计与实现}} +\fancyfoot[C]{\thepage} +\renewcommand{\headrulewidth}{0.4pt} +\renewcommand{\footrulewidth}{0.4pt} + +% --- 标题信息 --- +\title{\vspace{-2cm}\textbf{实验二：RISC-V CPU 中断处理机制设计与实现}} +\author{朱梓涵 \\ 学号：24325356} +\date{\today} + +% --- 代码高亮风格定义 (Solarized-light) --- +\definecolor{sol-base03}{HTML}{002b36} +\definecolor{sol-base02}{HTML}{073642} +\definecolor{sol-base01}{HTML}{586e75} +\definecolor{sol-base00}{HTML}{657b83} +\definecolor{sol-base0}{HTML}{839496} +\definecolor{sol-base1}{HTML}{93a1a1} +\definecolor{sol-base2}{HTML}{eee8d5} +\definecolor{sol-base3}{HTML}{fdf6e3} +\definecolor{sol-yellow}{HTML}{b58900} +\definecolor{sol-orange}{HTML}{cb4b16} +\definecolor{sol-red}{HTML}{dc322f} +\definecolor{sol-magenta}{HTML}{d33682} +\definecolor{sol-violet}{HTML}{6c71c4} +\definecolor{sol-blue}{HTML}{268bd2} +\definecolor{sol-cyan}{HTML}{2aa198} +\definecolor{sol-green}{HTML}{859900} +\lstdefinestyle{ScalaChiselStyle}{commentstyle=\color{sol-base01}\itshape,keywordstyle=\color{sol-green}\bfseries,stringstyle=\color{sol-cyan},basicstyle=\ttfamily\small,breakatwhitespace=false,breaklines=true,captionpos=b,keepspaces=true,numbers=none,showspaces=false,showstringspaces=false,showtabs=false,tabsize=2,frame=single,rulecolor=\color{black},morekeywords={when, Mux, MuxLookup, IndexedSeq, U, io, :=, object, val, def, class, override, package, import, extends, with, Bits, UInt, SInt},extendedchars=false,literate={:}{{\color{sol-base02}:}}1} +\lstdefinestyle{CStyle}{commentstyle=\color{sol-base01}\itshape,keywordstyle=\color{sol-orange}\bfseries,stringstyle=\color{sol-cyan},basicstyle=\ttfamily\small,breakatwhitespace=false,breaklines=true,captionpos=b,keepspaces=true,numbers=none,showspaces=false,showstringspaces=false,showtabs=false,tabsize=2,frame=single,rulecolor=\color{black},extendedchars=false} +\lstset{style=ScalaChiselStyle} + +% --- 图片计数器与章节联动 --- +\counterwithin{figure}{section} +\counterwithin{table}{section} + +% --- 文档开始 --- +\begin{document} + +\maketitle +\thispagestyle{empty} + +\section{实验目的} +本实验旨在为已实现的单周期 RISC-V CPU 增加中断与异常处理功能，深入理解现代处理器如何响应并处理非顺序控制流事件。实验目标包括： +\begin{enumerate}[label=\arabic*.] + \item 设计并实现控制状态寄存器 (CSR) 模块，支持 CSR 指令的读写操作。 + \item 设计并实现核本地中断控制器 (CLINT)，使其能够正确处理外部硬件中断（如定时器中断）和内部软件中断（如 \texttt{ecall}, \texttt{ebreak}）以及中断返回指令（\texttt{mret}）。 + \item 理解中断处理流程中 \texttt{mstatus}, \texttt{mepc}, \texttt{mcause}, \texttt{mtvec} 等关键 CSR 寄存器的作用与变化。 + \item 学习通过 Chisel 测试用例和波形图分析，验证复杂的中断处理逻辑的正确性。 +\end{enumerate} + +\section{实验环境} +\begin{itemize} + \item \textbf{操作系统}: Windows 11 + \item \textbf{开发工具}: Visual Studio Code + \item \textbf{构建工具}: SBT + \item \textbf{仿真与测试}: Verilator, GTKWave, MSYS2 (MinGW64) +\end{itemize} + +\section{模块实现与分析} +本次实验的核心是新增 \texttt{CSR} 和 \texttt{CLINT} 模块，并对 \texttt{Execute} 模块进行扩展以支持 CSR 指令。 + +\subsection{CSR 模块} +CSR (Control and Status Register) 模块是 CPU 的状态管理中心，负责存储和更新如 \texttt{mstatus}, \texttt{mepc} 等关键状态寄存器。 +\begin{itemize} + \item \textbf{实现要点}： + \begin{enumerate} + \item \textbf{独立寄存器与查找表}：将重要的 CSR（如 \texttt{mstatus}）实现为独立的物理寄存器，并通过一个查找表 \texttt{regLUT} 响应读请求，设计清晰且高效。 + \item \textbf{写操作优先级}：写入逻辑必须处理来自 CLINT（中断/异常事件）和 Execute（CSR指令）的并发写请求。设计中，CLINT 的写入拥有最高优先级，确保了中断处理的原子性。 + \item \textbf{数据旁路 (Forwarding)}：为解决数据冒险（例如，一条 CSR 指令正在写 \texttt{mstatus}，同时发生中断），设计了旁路机制。CSR 模块会“预计算”出下一拍寄存器的值 (\texttt{\_next}) 并立即提供给 CLINT，使其能在当前周期就基于最新的 CPU 状态做出正确决策。 + \end{enumerate} +\end{itemize} + +\subsubsection{代码实现} +\begin{lstlisting}[caption={CSR 模块的写入优先级与旁路逻辑}, label={lst:csr_logic}] + val mstatus_next = Mux(io.reg_write_enable_id && + io.reg_write_address_id === CSRRegister.MSTATUS, + io.reg_write_data_ex, mstatus) + val mepc_next = Mux(io.reg_write_enable_id && + io.reg_write_address_id === CSRRegister.MEPC, + io.reg_write_data_ex, mepc) + + io.clint_access_bundle.mstatus := mstatus_next + io.clint_access_bundle.mepc := mepc_next + + when(io.clint_access_bundle.direct_write_enable) { + mstatus := io.clint_access_bundle.mstatus_write_data + mepc := io.clint_access_bundle.mepc_write_data + mcause := io.clint_access_bundle.mcause_write_data + }.elsewhen(io.reg_write_enable_id) { + when(io.reg_write_address_id === CSRRegister.MSTATUS) { + mstatus := io.reg_write_data_ex + } + } +\end{lstlisting} + +\subsection{CLINT 模块} +CLINT (Core-Local Interrupt Controller) 是中断处理的“决策中心”，负责监视 CPU 状态，判断中断/异常事件，并生成控制信号来改变 CPU 的执行流和状态。 +\begin{itemize} + \item \textbf{实现要点}： + \begin{enumerate} + \item \textbf{事件检测}：通过组合逻辑判断外部中断信号 (\texttt{interrupt\_flag}) 和特定指令（\texttt{mret}, \texttt{ecall}, \texttt{ebreak}）的发生。 + \item \textbf{状态更新计算}：根据发生的事件类型，精确计算 \texttt{mepc}, \texttt{mcause}, \texttt{mstatus} 这三个 CSR 寄存器需要更新成的新值。 + \item \textbf{PC 重定向}：当陷阱 (trap) 发生或 \texttt{mret} 执行时，置位 \texttt{interrupt\_assert} 标志，并提供新的 PC 地址（中断时为 \texttt{mtvec}，返回时为 \texttt{mepc}）。 + \item \textbf{处理优先级}：通过一个 \texttt{when-elsewhen-otherwise} 结构明确了事件处理的优先级：外部硬件中断 > \texttt{mret} > \texttt{ecall} > \texttt{ebreak}。 + \end{enumerate} +\end{itemize} + +\subsubsection{代码实现} +\begin{lstlisting}[caption={CLINT 模块处理硬件中断的核心逻辑}, label={lst:clint_logic}] + val interrupt_enable = io.csr_bundle.mstatus(3) + val instruction_address = Mux( + io.jump_flag, + io.jump_address, + io.instruction_address + 4.U + ) + val mstatus = io.csr_bundle.mstatus + val mie = mstatus(3) + + when(io.interrupt_flag =/= InterruptCode.None && interrupt_enable) { + io.interrupt_assert := true.B + io.csr_bundle.direct_write_enable := true.B + io.interrupt_handler_address := io.csr_bundle.mtvec + io.csr_bundle.mepc_write_data := instruction_address + io.csr_bundle.mcause_write_data := "h80000007".U + val new_mpie = mie << 7 + io.csr_bundle.mstatus_write_data := + (mstatus & (~(1.U << 3)).asUInt) | new_mpie | (3.U << 11) + }.elsewhen(io.instruction === InstructionsRet.mret) { + } +\end{lstlisting} + +\section{测试与结果分析} + +\subsection{CLINTCSRTest: 软件中断 \texttt{ecall} 测试分析} + +\subsubsection{测试机制简述} +该测试旨在验证 CPU 对 \texttt{ecall} (Environment Call) 指令的响应是否正确。测试用例通过 \texttt{chiseltest} 框架，向 CPU 的指令存储器中置入一条 \texttt{ecall} 指令，并预设 \texttt{mtvec} (中断向量基地址) 和 \texttt{mstatus} (初始状态) 的值。 +测试通过以下几点验证 CLINT 和 CSR 的功能： +\begin{enumerate} + \item \textbf{输入信号}： + \begin{itemize} + \item \texttt{instruction}: 输入 \texttt{ecall} 的机器码 \texttt{0x00000073}。 + \item \texttt{instruction\_address}: 假设为 \texttt{0x0}。 + \item \texttt{csr\_bundle.mstatus}: 初始值，确保中断使能位 MIE (第3位) 为1。 + \item \texttt{csr\_bundle.mtvec}: 预设的中断处理程序入口地址，例如 \texttt{0x1000}。 + \end{itemize} + \item \textbf{功能测试点}： + \begin{itemize} + \item \textbf{CLINT}：是否能正确识别 \texttt{ecall} 指令，并计算出正确的 \texttt{mepc} (应为 \texttt{0x4})、\texttt{mcause} (应为 \texttt{11}) 和新的 \texttt{mstatus} 值（MIE 关闭，旧 MIE 备份到 MPIE）。 + \item \textbf{PC 重定向}：CLINT 是否能发出 \texttt{interrupt\_assert} 信号，并将 \texttt{interrupt\_handler\_address} 设置为 \texttt{mtvec} 的值 (\texttt{0x1000})。 + \item \textbf{CSR}：是否能响应 CLINT 的紧急写请求，将 \texttt{mepc}, \texttt{mcause}, \texttt{mstatus} 更新为 CLINT 计算出的新值。 + \end{itemize} +\end{enumerate} + +\subsubsection{波形图分析} +\begin{figure}[htbp] + \centering + % \includegraphics[width=\textwidth]{your/ecall_waveform.png} % <<<--- 在这里插入你的 ecall 波形图 + \caption{\texttt{ecall} 指令中断处理过程波形图} + \label{fig:ecall_waveform} +\end{figure} +图 \ref{fig:ecall_waveform} 展示了 CPU 执行 \texttt{ecall} 指令的单周期过程。 +\begin{enumerate} + \item[T0] \textbf{事件触发}：在时钟上升沿之前，取指模块获取到指令 \texttt{clint\_io\_instruction} 为 \texttt{0x00000073} (\texttt{ecall})，其地址 \texttt{clint\_io\_instruction\_address} 为 \texttt{0x0}。 + \item[T1] \textbf{CLINT 响应与计算 (组合逻辑)}： + \begin{itemize} + \item CLINT 模块检测到 \texttt{ecall} 指令。根据其内部的 \texttt{elsewhen(io.instruction === InstructionsEnv.ecall)} 分支，它开始计算。 + \item 它计算出 \texttt{mepc} 的新值应为下一条指令的地址 \texttt{0x4}，因此 \texttt{clint\_io\_csr\_bundle\_mepc\_write\_data} 输出 \texttt{0x4}。 + \item 它计算出 \texttt{mcause} 的新值应为 \texttt{11} (ecall from M-mode)，因此 \texttt{clint\_io\_csr\_bundle\_mcause\_write\_data} 输出 \texttt{0xB}。 + \item 它计算出新的 \texttt{mstatus}，将 MIE 位清零，并将旧的 MIE 位备份到 MPIE 位。 + \item CLINT 将 \texttt{clint\_io\_interrupt\_assert} 置为高电平 (1)，表示需要重定向 PC。 + \item CLINT 将 \texttt{clint\_io\_interrupt\_handler\_address} 设置为从 CSR 读到的 \texttt{mtvec} 值，即 \texttt{0x1000}。 + \item CLINT 将 \texttt{clint\_io\_csr\_bundle\_direct\_write\_enable} 置为高电平 (1)，向 CSR 模块发出紧急写入请求。 + \end{itemize} + \item[T2] \textbf{状态更新与 PC 跳转 (时序逻辑)}： + \begin{itemize} + \item 在下一个时钟上升沿，CPU 顶层模块根据 \texttt{clint\_io\_interrupt\_assert} 信号，选择 \texttt{clint\_io\_interrupt\_handler\_address} (\texttt{0x1000}) 作为下一周期的 PC 值。 + \item 同时，CSR 模块根据其最高优先级的 \texttt{when(io.clint\_access\_bundle.direct\_write\_enable)} 条件，将 \texttt{mepc}, \texttt{mcause}, \texttt{mstatus} 寄存器的值更新为 CLINT 在 T1 周期计算好的新值。 + \end{itemize} +\end{enumerate} +这个过程完整地展示了从软件中断发生到 CPU 保存现场、跳转至处理程序的全部关键步骤，波形图上的信号变化与预期完全一致。 + + +\subsection{CPUTest: SimpleTrapTest 分析} + +\subsubsection{测试程序 (\texttt{simpletest.c}) 原理} +该测试程序旨在验证 CPU 在中断发生后，能够正确地跳转到中断处理程序，在处理程序中通过读取 \texttt{mcause} 和 \texttt{mepc} 来判断中断原因和来源，并最终通过 \texttt{mret} 指令正确返回到被中断的程序点继续执行。 +\begin{itemize} + \item \textbf{主程序流程}：\texttt{main} 函数设置 \texttt{mtvec} 指向中断处理函数 \texttt{trap\_handler}，然后通过内联汇编执行一条 \texttt{ecall} 指令来主动触发一个软件中断。 + \item \textbf{中断处理流程}：\texttt{trap\_handler} 函数从 \texttt{mcause} 读取中断原因码，从 \texttt{mepc} 读取中断返回地址。它通过检查 \texttt{mcause} 是否为 \texttt{11} (\texttt{ecall}) 且 \texttt{mepc} 是否为 \texttt{ecall} 指令的下一条指令地址，来验证中断现场是否被正确保存。如果验证通过，它会将一个标志值（\texttt{0xbeef}）写入内存特定地址，然后执行 \texttt{mret} 返回。 + \item \textbf{正确性验证}：\texttt{main} 函数在 \texttt{ecall} 返回后，会检查内存中的那个特定地址。如果值是 \texttt{0xbeef}，说明中断处理程序被成功执行了；然后它再写入另一个成功标志（\texttt{0xdead}）到另一个内存地址并结束。Chisel 测试最终会检查内存中是否存在 \texttt{0xdead} 这个值，以此判断整个流程是否成功。 +\end{itemize} + +\subsubsection{波形图分析} + +\begin{figure}[htbp] + \centering + % \includegraphics[width=\textwidth]{your/simpletrap_waveform.png} % <<<--- 在这里插入你的 simpletrap 波形图 + \caption{\texttt{simpletest.c} 程序成功执行的关键信号波形} + \label{fig:simpletrap_waveform} +\end{figure} + +要证明该程序成功执行，需要在波形图上找到以下连续的关键事件： +\begin{enumerate} + \item \textbf{设置 \texttt{mtvec}}：在程序初期，会有一条 \texttt{csrrw} 指令将 \texttt{trap\_handler} 的地址写入 \texttt{mtvec} 寄存器。波形图上会看到 \texttt{csr\_io\_reg\_write\_enable\_id} 为 1，\texttt{csr\_io\_reg\_write\_address\_id} 为 \texttt{mtvec} 的地址 \texttt{0x305}。 + \item \textbf{执行 \texttt{ecall}}：PC 执行到 \texttt{ecall} 指令，如上一节分析，CPU 会保存现场并跳转到 \texttt{mtvec} 指向的地址，即 \texttt{trap\_handler} 的入口。 + \item \textbf{执行 \texttt{trap\_handler}}：PC 开始执行中断处理程序中的指令。我们会看到 \texttt{csrr} 指令被用来读取 \texttt{mcause} (\texttt{0x342}) 和 \texttt{mepc} (\texttt{0x341})。 + \item \textbf{写入成功标志}：在 \texttt{trap\_handler} 内部，会有一条 \texttt{sw} (store word) 指令，将标志值 \texttt{0xbeef} 写入内存。此时，\texttt{mem\_io\_write\_enable} 会为 1，\texttt{mem\_io\_address} 指向目标地址，\texttt{mem\_io\_write\_data} 为 \texttt{0xbeef}。 + \item \textbf{执行 \texttt{mret}}：\texttt{trap\_handler} 的最后一条指令是 \texttt{mret}。CLINT 会再次响应，这次 PC 会被设置为之前保存在 \texttt{mepc} 中的值，CPU 返回主程序。 + \item \textbf{写入最终标志}：主程序返回后，执行最后的 \texttt{sw} 指令，将 \texttt{0xdead} 写入内存。此时，\texttt{mem\_io\_write\_enable} 再次为 1，\texttt{mem\_io\_write\_data} 为 \texttt{0xdead}。 +\end{enumerate} +在波形图上能按顺序找到这 6 个关键事件，就足以证明 CPU 完整且正确地执行了中断处理与返回的全过程。 + +\subsection{CPU、操作系统与定时器中断协作过程} +假如我们的 CPU 上运行着一个简单的操作系统，当中断发生时，硬件 (CPU) 和软件 (OS) 会进行一次精密的“协作舞蹈”来完成处理。 +\begin{enumerate} + \item \textbf{OS 初始化 (启动阶段)}：操作系统在启动过程中，会执行特权指令（如 \texttt{csrrw}）来初始化中断处理机制。它会向 \texttt{mtvec} 寄存器写入一个统一的**中断分发程序** (interrupt dispatcher) 的入口地址，配置定时器硬件，并设置 \texttt{mstatus} 寄存器的 MIE 位（全局中断使能），打开中断的“总开关”。 + \item \textbf{硬件响应 (定时器中断发生)}：定时器硬件在倒计时结束后，向 CPU 发送中断信号。CPU 的 CLINT 模块检测到该信号，并且发现 \texttt{mstatus.MIE} 为 1。\textbf{CPU (硬件) 自动执行以下原子操作}： + \begin{enumerate} + \item 将 \texttt{mstatus.MIE} 位的值备份到 \texttt{mstatus.MPIE} 位，然后将 \texttt{mstatus.MIE} 清零，以防止中断嵌套。 + \item 将当前 PC 的值（下一条指令的地址）存入 \texttt{mepc} 寄存器。 + \item 根据中断源，在 \texttt{mcause} 寄存器中写入原因码（例如 \texttt{0x80000007}）。 + \item 读取 \texttt{mtvec} 寄存器的值，并强制将 PC 设置为该值。 + \end{enumerate} + \item \textbf{软件处理 (操作系统接管)}：CPU 的执行流跳转到了操作系统预设的**中断分发程序**。该程序首先保存用户程序的上下文（通用寄存器）到内存。然后，它读取 \texttt{mcause} 寄存器，发现原因是定时器中断，于是调用内核中专门的**定时器中断服务例程 (Timer ISR)**。Timer ISR 执行其核心任务（如更新系统时间、任务调度），并重新配置定时器。 + \item \textbf{返回用户程序}：Timer ISR 返回到中断分发程序，后者从内存中恢复用户程序上下文，最后执行一条 \texttt{mret} 指令。\textbf{CPU (硬件) 再次自动执行原子操作}： + \begin{enumerate} + \item 将 \texttt{mstatus.MPIE} 的值恢复到 \texttt{mstatus.MIE}，重新打开全局中断。 + \item 将 \texttt{mepc} 中保存的地址加载回 PC。 + \end{enumerate} +\end{enumerate} +至此，CPU 无缝地返回到被中断的用户程序继续执行，整个过程体现了硬件提供机制、软件实现策略的经典设计思想。 + +\subsection{实验改进建议} +\begin{enumerate} + \item \textbf{问题：Windows 环境配置复杂，缺少明确指引。} + + 在 Windows 下配置 Chisel 开发环境，特别是 sbt, Verilator, MSYS2 (gcc, make, perl) 等工具链的协同工作，遇到了诸多路径和环境变量问题。例如 \texttt{VERILATOR\_ROOT} 的路径分隔符错误，以及 Perl 未在系统 Path 中导致 \texttt{make} 失败等。 + \begin{itemize} + \item \textbf{建议}：实验指导可以提供一个专门针对 Windows + MSYS2 环境的详细配置教程，包括每个所需工具的安装命令、必须设置的环境变量（\texttt{VERILATOR\_ROOT}, \texttt{Path}）及其正确格式，并提供验证步骤（如运行 \texttt{verilator --version}, \texttt{perl --version}）。 + \end{itemize} + + \item \textbf{问题：CSR 指令的测试特化行为难以理解。} + + 在 \texttt{Execute.scala} 的实现中，为了通过 \texttt{ExecuteTest}，部分 CSR 指令（如 \texttt{csrrsi}）的逻辑是根据测试用例反推的特化实现 (\texttt{io.csr\_reg\_read\_data | 8.U})，而非完全符合 RISC-V 手册的标准行为。这在初次实现时会造成困惑。 + \begin{itemize} + \item \textbf{建议}：在实验指导或测试文件的注释中，明确指出某些测试用例是为了教学目的或简化而设计的，其行为可能与标准手册有细微差别，并简要说明"特化"的逻辑，能帮助学生更好地聚焦于实验核心，避免在细节上产生误解。 + \end{itemize} +\end{enumerate} + +\section{实验结论} +本次实验，我成功地为单周期 CPU 添加了完整的中断处理功能。通过设计 CSR 和 CLINT 模块，我深入学习了 RISC-V 的特权架构和中断处理流程，对 \texttt{mstatus}, \texttt{mepc}, \texttt{mcause} 等核心 CSR 的作用有了实践层面的深刻理解。解决 Windows 环境配置难题和调试复杂中断逻辑的过程，极大地锻炼了我分析问题和解决问题的能力。通过将理论知识与硬件实现、软件测试相结合，我不仅验证了 CPU 设计的正确性，也对操作系统与硬件的交互机制有了更具体的认识，为未来更深入的系统级学习打下了坚实的基础。 + +\end{document} diff --git a/lab2/成功截图/sbt.png b/lab2/成功截图/sbt.png new file mode 100644 index 0000000..6627790 Binary files /dev/null and b/lab2/成功截图/sbt.png differ diff --git a/lab3/src/main/scala/riscv/core/PipelineRegister.scala b/lab3/src/main/scala/riscv/core/PipelineRegister.scala index d736e53..73ff71d 100644 --- a/lab3/src/main/scala/riscv/core/PipelineRegister.scala +++ b/lab3/src/main/scala/riscv/core/PipelineRegister.scala @@ -25,6 +25,15 @@ class PipelineRegister(width: Int = Parameters.DataBits, defaultValue: UInt = 0. val out = Output(UInt(width.W)) }) // Lab3(PipelineRegister) - io.out := 0.U + val register = RegInit(defaultValue) + + when(io.flush) { + register := defaultValue + }.elsewhen(io.stall) { + }.otherwise { + register := io.in + } + + io.out := register // Lab3(PipelineRegister) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala b/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala index b4b6ade..2cf6dc4 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala @@ -34,10 +34,27 @@ class Control extends Module { val if2id_stall = Output(Bool()) }) + // Lab3(Final) - io.if2id_flush := false.B - io.id2ex_flush := false.B - io.pc_stall := false.B - io.if2id_stall := false.B + val stall = Wire(Bool()) + + val load_use_hazard = io.memory_read_enable_ex && io.rd_ex =/= 0.U && + (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) + + val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U && + !io.memory_read_enable_ex && // 确保不是load-use hazard + (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) + // 最终的阻塞条件 + stall := load_use_hazard || id_jump_needs_ex_alu + // 只有在流水线不被阻塞时，跳转信号（flush）才应该生效。 + val flush = io.jump_flag && !stall + // 最终输出 + io.pc_stall := stall + io.if2id_stall := stall + io.if2id_flush := flush + + // 只有在阻塞时，才需要清空ID/EX来插入气泡。 + // 跳转引起的清空只作用于IF/ID。 + io.id2ex_flush := stall // Lab3(Final) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala b/lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala index 1014476..4964ecc 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala @@ -41,9 +41,24 @@ class Forwarding extends Module { }) // Lab3(Final) - io.reg1_forward_id := 0.U - io.reg2_forward_id := 0.U - io.reg1_forward_ex := 0.U - io.reg2_forward_ex := 0.U + val ex_mem_hazard_rs1 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_ex) + val ex_mem_hazard_rs2 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs2_ex) + val ex_wb_hazard_rs1 = io.reg_write_enable_wb && io.rd_wb =/= 0.U && (io.rd_wb === io.rs1_ex) + val ex_wb_hazard_rs2 = io.reg_write_enable_wb && io.rd_wb =/= 0.U && (io.rd_wb === io.rs2_ex) + io.reg1_forward_ex := Mux(ex_mem_hazard_rs1, ForwardingType.ForwardFromMEM, + Mux(ex_wb_hazard_rs1, ForwardingType.ForwardFromWB, ForwardingType.NoForward)) + io.reg2_forward_ex := Mux(ex_mem_hazard_rs2, ForwardingType.ForwardFromMEM, + Mux(ex_wb_hazard_rs2, ForwardingType.ForwardFromWB, ForwardingType.NoForward)) + // --- 旁路到 ID 阶段 --- + val id_mem_hazard_rs1 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id) + val id_mem_hazard_rs2 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs2_id) + // 当MEM阶段转发时，就不需要再看WB阶段了 + val id_wb_hazard_rs1 = io.reg_write_enable_wb && io.rd_wb =/= 0.U && !id_mem_hazard_rs1 && (io.rd_wb === io.rs1_id) + val id_wb_hazard_rs2 = io.reg_write_enable_wb && io.rd_wb =/= 0.U && !id_mem_hazard_rs2 && (io.rd_wb === io.rs2_id) + io.reg1_forward_id := Mux(id_mem_hazard_rs1, ForwardingType.ForwardFromMEM, + Mux(id_wb_hazard_rs1, ForwardingType.ForwardFromWB, ForwardingType.NoForward)) + io.reg2_forward_id := Mux(id_mem_hazard_rs2, ForwardingType.ForwardFromMEM, + Mux(id_wb_hazard_rs2, ForwardingType.ForwardFromWB, ForwardingType.NoForward)) + // Lab3(Final) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_final/InstructionDecode.scala b/lab3/src/main/scala/riscv/core/fivestage_final/InstructionDecode.scala index 11a92f2..41e72c3 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_final/InstructionDecode.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_final/InstructionDecode.scala @@ -171,8 +171,10 @@ class InstructionDecode extends Module { val rs2 = io.instruction(24, 20) // Lab3(Final) ID rs - io.regs_reg1_read_address := rs1 - io.regs_reg2_read_address := rs2 + val rs1_used = opcode =/= Instructions.lui && opcode =/= Instructions.auipc && opcode =/= Instructions.jal + val rs2_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.S || opcode === InstructionTypes.B + io.regs_reg1_read_address := Mux(rs1_used, rs1, 0.U) + io.regs_reg2_read_address := Mux(rs2_used, rs2, 0.U) // Lab3(Final) ID rs End io.ex_immediate := MuxLookup( opcode, @@ -211,8 +213,11 @@ class InstructionDecode extends Module { ) ) // Lab3(Final) ID rd - io.ex_reg_write_enable := false.B - io.ex_reg_write_address := rd + val rd_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.I || opcode === InstructionTypes.L || + opcode === Instructions.lui || opcode === Instructions.auipc || opcode === Instructions.jal || + opcode === Instructions.jalr || opcode === Instructions.csr + io.ex_reg_write_enable := rd_used + io.ex_reg_write_address := Mux(rd_used, rd, 0.U) // Lab3(Final) ID rd End io.ex_csr_address := io.instruction(31, 20) io.ex_csr_write_enable := (opcode === Instructions.csr) && ( @@ -222,10 +227,52 @@ class InstructionDecode extends Module { ) // Lab3(Final) - io.ctrl_jump_instruction := false.B - io.clint_jump_flag := false.B - io.clint_jump_address := 0.U - io.if_jump_flag := false.B - io.if_jump_address := 0.U +// io.ctrl_jump_instruction := false.B +// io.clint_jump_flag := false.B +// io.clint_jump_address := 0.U +// io.if_jump_flag := false.B +// io.if_jump_address := 0.U + val reg1_data = MuxLookup(io.reg1_forward, io.reg1_data)( + Seq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + val reg2_data = MuxLookup(io.reg2_forward, io.reg2_data)( + Seq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + val is_jump_instruction = opcode === Instructions.jal || opcode === Instructions.jalr || opcode === InstructionTypes.B + io.ctrl_jump_instruction := is_jump_instruction + val jump_condition_met = + (opcode === Instructions.jal) || + (opcode === Instructions.jalr) || + (opcode === InstructionTypes.B) && MuxLookup( + funct3, + false.B, + IndexedSeq( + InstructionsTypeB.beq -> (reg1_data === reg2_data), + InstructionsTypeB.bne -> (reg1_data =/= reg2_data), + InstructionsTypeB.blt -> (reg1_data.asSInt < reg2_data.asSInt), + InstructionsTypeB.bge -> (reg1_data.asSInt >= reg2_data.asSInt), + InstructionsTypeB.bltu -> (reg1_data < reg2_data), + InstructionsTypeB.bgeu -> (reg1_data >= reg2_data) + ) + ) + val jump_address = Mux( + opcode === Instructions.jalr, + (reg1_data.asSInt + io.ex_immediate.asSInt).asUInt, + (io.instruction_address.asSInt + io.ex_immediate.asSInt).asUInt + ) & (~1.U(Parameters.DataWidth)).asUInt // Ensure address is even + io.clint_jump_flag := jump_condition_met + io.clint_jump_address := jump_address + io.if_jump_flag := jump_condition_met || io.interrupt_assert + io.if_jump_address := Mux( + io.interrupt_assert, + io.interrupt_handler_address, + jump_address + ) // Lab3(Final) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala b/lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala index 4ce092a..fabe4a3 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala @@ -32,9 +32,17 @@ class Control extends Module { }) // Lab3(Forward) - io.if2id_flush := false.B - io.id2ex_flush := false.B - io.pc_stall := false.B - io.if2id_stall := false.B +// io.if2id_flush := false.B +// io.id2ex_flush := false.B +// io.pc_stall := false.B + // io.if2id_stall := false.B + val load_use_hazard = io.memory_read_enable_ex && + (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) && + io.rd_ex =/= 0.U + val flush = io.jump_flag + io.pc_stall := load_use_hazard && !flush + io.if2id_stall := load_use_hazard && !flush + io.if2id_flush := flush + io.id2ex_flush := flush || load_use_hazard // Lab3(Forward) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_forward/Execute.scala b/lab3/src/main/scala/riscv/core/fivestage_forward/Execute.scala index 32a7fdc..c0b7b09 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_forward/Execute.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_forward/Execute.scala @@ -61,8 +61,18 @@ class Execute extends Module { alu.io.func := alu_ctrl.io.alu_funct // Lab3(Forward) - val reg1_data = 0.U - val reg2_data = 0.U + val reg1_data = MuxLookup(io.reg1_forward, io.reg1_data)( + Seq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + val reg2_data = MuxLookup(io.reg2_forward, io.reg2_data)( + Seq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) // Lab3(Forward) End alu.io.op1 := Mux( diff --git a/lab3/src/main/scala/riscv/core/fivestage_forward/Forwarding.scala b/lab3/src/main/scala/riscv/core/fivestage_forward/Forwarding.scala index e644842..19c36a7 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_forward/Forwarding.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_forward/Forwarding.scala @@ -38,7 +38,19 @@ class Forwarding extends Module { }) // Lab3(Forward) - io.reg1_forward_ex := 0.U - io.reg2_forward_ex := 0.U +// io.reg1_forward_ex := 0.U +// io.reg2_forward_ex := 0.U + io.reg1_forward_ex := ForwardingType.NoForward + io.reg2_forward_ex := ForwardingType.NoForward + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs1_ex) { + io.reg1_forward_ex := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs1_ex) { + io.reg1_forward_ex := ForwardingType.ForwardFromWB + } + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs2_ex) { + io.reg2_forward_ex := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs2_ex) { + io.reg2_forward_ex := ForwardingType.ForwardFromWB + } // Lab3(Forward) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_forward/InstructionDecode.scala b/lab3/src/main/scala/riscv/core/fivestage_forward/InstructionDecode.scala index 249eb23..c62fb4a 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_forward/InstructionDecode.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_forward/InstructionDecode.scala @@ -157,8 +157,12 @@ class InstructionDecode extends Module { val rs2 = io.instruction(24, 20) // Lab3(Forward) ID rs - io.regs_reg1_read_address := rs1 - io.regs_reg2_read_address := rs2 +// io.regs_reg1_read_address := rs1 +// io.regs_reg2_read_address := rs2 + val rs1_used = opcode =/= Instructions.lui && opcode =/= Instructions.auipc && opcode =/= Instructions.jal + val rs2_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.S || opcode === InstructionTypes.B + io.regs_reg1_read_address := Mux(rs1_used, rs1, 0.U) + io.regs_reg2_read_address := Mux(rs2_used, rs2, 0.U) // Lab3(Forward) ID rs End io.ex_immediate := MuxLookup( opcode, @@ -197,8 +201,13 @@ class InstructionDecode extends Module { ) ) // Lab3(Forward) ID rd - io.ex_reg_write_enable := false.B - io.ex_reg_write_address := rd +// io.ex_reg_write_enable := false.B +// io.ex_reg_write_address := rd + val rd_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.I || opcode === InstructionTypes.L || + opcode === Instructions.lui || opcode === Instructions.auipc || opcode === Instructions.jal || + opcode === Instructions.jalr || opcode === Instructions.csr + io.ex_reg_write_enable := rd_used + io.ex_reg_write_address := Mux(rd_used, rd, 0.U) // Lab3(Forward) ID rd End io.ex_csr_address := io.instruction(31, 20) io.ex_csr_write_enable := (opcode === Instructions.csr) && ( diff --git a/lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala b/lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala index 518e8b5..7b7ccb9 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala @@ -34,10 +34,18 @@ class Control extends Module { }) // Lab3(Stall) - io.if2id_flush := false.B - io.id2ex_flush := false.B - - io.pc_stall := false.B - io.if2id_stall := false.B +// io.if2id_flush := false.B +// io.id2ex_flush := false.B +// +// io.pc_stall := false.B +// io.if2id_stall := false.B + val hazard_from_ex = io.reg_write_enable_ex && io.rd_ex =/= 0.U && (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) + val hazard_from_mem = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id || io.rd_mem === io.rs2_id) + val stall = hazard_from_ex || hazard_from_mem + val flush = io.jump_flag + io.pc_stall := stall && !flush + io.if2id_stall := stall && !flush + io.if2id_flush := flush + io.id2ex_flush := flush || stall // Lab3(Stall) End } diff --git a/lab3/src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala b/lab3/src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala index 4edffb4..e1128a5 100644 --- a/lab3/src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala +++ b/lab3/src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala @@ -157,8 +157,10 @@ class InstructionDecode extends Module { val rs2 = io.instruction(24, 20) // Lab3(Stall) ID rs - io.regs_reg1_read_address := rs1 - io.regs_reg2_read_address := rs2 + val rs1_used = opcode =/= Instructions.lui && opcode =/= Instructions.auipc && opcode =/= Instructions.jal + val rs2_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.S || opcode === InstructionTypes.B + io.regs_reg1_read_address := Mux(rs1_used, rs1, 0.U) + io.regs_reg2_read_address := Mux(rs2_used, rs2, 0.U) // Lab3(Stall) ID rs End io.ex_immediate := MuxLookup( opcode, @@ -197,8 +199,11 @@ class InstructionDecode extends Module { ) ) // Lab3(Stall) ID rd - io.ex_reg_write_enable := false.B - io.ex_reg_write_address := rd + val rd_used = opcode === InstructionTypes.RM || opcode === InstructionTypes.I || opcode === InstructionTypes.L || + opcode === Instructions.lui || opcode === Instructions.auipc || opcode === Instructions.jal || + opcode === Instructions.jalr || opcode === Instructions.csr + io.ex_reg_write_enable := rd_used + io.ex_reg_write_address := Mux(rd_used, rd, 0.U) // Lab3(Stall) ID rd End io.ex_csr_address := io.instruction(31, 20) io.ex_csr_write_enable := (opcode === Instructions.csr) && ( diff --git a/lab3/src/main/scala/riscv/core/threestage/CPU.scala b/lab3/src/main/scala/riscv/core/threestage/CPU.scala index d35cd69..5a9fd25 100644 --- a/lab3/src/main/scala/riscv/core/threestage/CPU.scala +++ b/lab3/src/main/scala/riscv/core/threestage/CPU.scala @@ -32,8 +32,11 @@ class CPU extends Module { val csr_regs = Module(new CSR) // Lab3(ThreeStage) - if2id.io.flush := false.B - id2ex.io.flush := false.B +// if2id.io.flush := false.B +// id2ex.io.flush := false.B + ctrl.io.jump_flag_ex := ex.io.if_jump_flag + if2id.io.flush := ctrl.io.if2id_flush + id2ex.io.flush := ctrl.io.id2ex_flush // Lab3(ThreeStage) End regs.io.write_enable := id2ex.io.output_regs_write_enable diff --git a/lab3/src/main/scala/riscv/core/threestage/Control.scala b/lab3/src/main/scala/riscv/core/threestage/Control.scala index 620c1c0..05cfcc5 100644 --- a/lab3/src/main/scala/riscv/core/threestage/Control.scala +++ b/lab3/src/main/scala/riscv/core/threestage/Control.scala @@ -18,5 +18,13 @@ import chisel3._ class Control extends Module { // Lab3(ThreeStage) + val io = IO(new Bundle { + val jump_flag_ex = Input(Bool()) + val if2id_flush = Output(Bool()) + val id2ex_flush = Output(Bool()) + }) + val flush = io.jump_flag_ex + io.if2id_flush := flush + io.id2ex_flush := flush // Lab3(ThreeStage) End }