diff --git a/.gitignore b/.gitignore
index 3af21e4..cffe121 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,8 +1,13 @@
 target
 .vscode
 .metals
+.bloop
 **/test_run_dir
 
 # vivado stuffs
 **/*.jou
 **/*.log
+
+**/hello_z710-test
+**/riscv-z710-v2020
+.Xil
diff --git a/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala b/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala
index 084d614..6d950ae 100644
--- a/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala
@@ -18,7 +18,7 @@ import chisel3._
 import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 import riscv.TestAnnotations
-import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionDecode, InstructionTypes}
+import riscv.core.{ALUOp1Source, ALUOp2Source, RegWriteSource, InstructionDecode, InstructionTypes}
 
 class InstructionDecoderTest extends AnyFlatSpec with ChiselScalatestTester{
   behavior of "InstructionDecoder of Single Cycle CPU"