add file

lab1/Makefile

@@ -24,8 +24,12 @@ verilator-sim: verilator
 
 basys3:
 	sbt "runMain board.basys3.VerilogGenerator"
+	
 pynq:
 	sbt "runMain board.pynq.VerilogGenerator"
+	
+z710:
+	sbt "runMain board.z710.VerilogGenerator"
 
 bitstream-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl
@@ -35,6 +39,7 @@ program-basys3: bitstream-basys3
 
 vivado-sim-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl
+	
 bitstream-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl
 
@@ -43,5 +48,14 @@ program-pynq: bitstream-pynq
 
 vivado-sim-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source run_simulation.tcl
+	
+bitstream-z710: z710
+	cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl
 
-.PHONY: basys3 verilator test bitstream program verilator-sim vivado-sim
+program-z710: bitstream-z710
+	cd vivado/z710 && vivado -mode batch -source program_device.tcl
+
+vivado-sim-z710: z710
+	cd vivado/z710 && vivado -mode batch -source run_simulation.tcl
+
+.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim

lab1/src/main/scala/board/z710/z710/Top.scala

@@ -0,0 +1,119 @@
+package board.z710
+
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util._
+import chisel3.{ChiselEnum, _}
+
+// import circt.stage.ChiselStage
+import chisel3.stage.ChiselGeneratorAnnotation
+
+import bus._
+import peripheral._
+import riscv._
+import riscv.Parameters
+import riscv.core.CPU
+import javax.print.SimpleDoc
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, BusWait, Finished = Value
+}
+
+
+class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
+  // val binaryFilename = "say_goodbye.asmbin"
+  val io = IO(new Bundle {
+    // val switch = Input(UInt(16.W))
+
+    // val rgb = Output(UInt(12.W))
+
+    val led = Output(Bool())
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val uart = Module(new Uart(125_000_000, 115200))  // this freq is consistent with Zynq 7 PS UART module
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+
+  
+  val clock_freq = 100_000_000.U
+
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+
+  io.led := (led_count >= (clock_freq >> 1))
+
+
+}
+
+
+
+object VerilogGenerator extends App {
+    (new ChiselStage).execute(
+        Array("-X", "verilog", "--target-dir", "verilog/z710"), 
+        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
+    )
+    
+}

lab1/src/test/scala/riscv/BoardTest.scala

@@ -0,0 +1,25 @@
+package riscv
+
+import board.z710.Top
+
+import riscv.{Parameters, TestAnnotations}
+import chisel3._
+import chisel3.util.{is, switch}
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import board.z710.Top
+
+
+class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Board simulation"
+  it should "say goodbye " in {
+    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+

lab2/Makefile

@@ -24,8 +24,12 @@ verilator-sim: verilator
 
 basys3:
 	sbt "runMain board.basys3.VerilogGenerator"
+	
 pynq:
 	sbt "runMain board.pynq.VerilogGenerator"
+	
+z710:
+	sbt "runMain board.z710.VerilogGenerator"
 
 bitstream-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl
@@ -35,6 +39,7 @@ program-basys3: bitstream-basys3
 
 vivado-sim-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl
+	
 bitstream-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl
 
@@ -43,5 +48,14 @@ program-pynq: bitstream-pynq
 
 vivado-sim-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source run_simulation.tcl
+	
+bitstream-z710: z710
+	cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl
 
-.PHONY: basys3 verilator test bitstream program verilator-sim vivado-sim
+program-z710: bitstream-z710
+	cd vivado/z710 && vivado -mode batch -source program_device.tcl
+
+vivado-sim-z710: z710
+	cd vivado/z710 && vivado -mode batch -source run_simulation.tcl
+
+.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim

lab2/src/test/scala/riscv/BoardTest.scala

@@ -0,0 +1,25 @@
+package riscv
+
+import board.z710.Top
+
+import riscv.{Parameters, TestAnnotations}
+import chisel3._
+import chisel3.util.{is, switch}
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import board.z710.Top
+
+
+class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Board simulation"
+  it should "say goodbye " in {
+    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+

lab2/verilog/z710/z710/Top.scala

@@ -0,0 +1,119 @@
+package board.z710
+
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util._
+import chisel3.{ChiselEnum, _}
+
+// import circt.stage.ChiselStage
+import chisel3.stage.ChiselGeneratorAnnotation
+
+import bus._
+import peripheral._
+import riscv._
+import riscv.Parameters
+import riscv.core.CPU
+import javax.print.SimpleDoc
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, BusWait, Finished = Value
+}
+
+
+class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
+  // val binaryFilename = "say_goodbye.asmbin"
+  val io = IO(new Bundle {
+    // val switch = Input(UInt(16.W))
+
+    // val rgb = Output(UInt(12.W))
+
+    val led = Output(Bool())
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val uart = Module(new Uart(125_000_000, 115200))  // this freq is consistent with Zynq 7 PS UART module
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+
+  
+  val clock_freq = 100_000_000.U
+
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+
+  io.led := (led_count >= (clock_freq >> 1))
+
+
+}
+
+
+
+object VerilogGenerator extends App {
+    (new ChiselStage).execute(
+        Array("-X", "verilog", "--target-dir", "verilog/z710"), 
+        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
+    )
+    
+}

lab3/Makefile

@@ -24,8 +24,12 @@ verilator-sim: verilator
 
 basys3:
 	sbt "runMain board.basys3.VerilogGenerator"
+	
 pynq:
 	sbt "runMain board.pynq.VerilogGenerator"
+	
+z710:
+	sbt "runMain board.z710.VerilogGenerator"
 
 bitstream-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl
@@ -35,6 +39,7 @@ program-basys3: bitstream-basys3
 
 vivado-sim-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl
+	
 bitstream-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl
 
@@ -43,13 +48,14 @@ program-pynq: bitstream-pynq
 
 vivado-sim-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source run_simulation.tcl
+	
+bitstream-z710: z710
+	cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl
 
-arch-test: verilator
+program-z710: bitstream-z710
-	cp -r ../lab3 ~ && \
+	cd vivado/z710 && vivado -mode batch -source program_device.tcl
-	cd ~/riscv-arch-test && \
-	export TARGET_SIM=~/lab3/verilog/verilator/obj_dir/VTop && \
-	export TARGETDIR=~/lab3/riscv-target && \
-	export RISCV_TARGET=yatcpu && \
-    make
 
-.PHONY: basys3 verilator test bitstream program verilator-sim vivado-sim
+vivado-sim-z710: z710
+	cd vivado/z710 && vivado -mode batch -source run_simulation.tcl
+
+.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim

lab3/src/main/scala/board/z710/z710/Top.scala

@@ -0,0 +1,119 @@
+package board.z710
+
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util._
+import chisel3.{ChiselEnum, _}
+
+// import circt.stage.ChiselStage
+import chisel3.stage.ChiselGeneratorAnnotation
+
+import bus._
+import peripheral._
+import riscv._
+import riscv.Parameters
+import riscv.core.CPU
+import javax.print.SimpleDoc
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, BusWait, Finished = Value
+}
+
+
+class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
+  // val binaryFilename = "say_goodbye.asmbin"
+  val io = IO(new Bundle {
+    // val switch = Input(UInt(16.W))
+
+    // val rgb = Output(UInt(12.W))
+
+    val led = Output(Bool())
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val uart = Module(new Uart(125_000_000, 115200))  // this freq is consistent with Zynq 7 PS UART module
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+
+  
+  val clock_freq = 100_000_000.U
+
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+
+  io.led := (led_count >= (clock_freq >> 1))
+
+
+}
+
+
+
+object VerilogGenerator extends App {
+    (new ChiselStage).execute(
+        Array("-X", "verilog", "--target-dir", "verilog/z710"), 
+        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
+    )
+    
+}

lab3/src/test/scala/riscv/BoardTest.scala

@@ -0,0 +1,25 @@
+package riscv
+
+import board.z710.Top
+
+import riscv.{Parameters, TestAnnotations}
+import chisel3._
+import chisel3.util.{is, switch}
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import board.z710.Top
+
+
+class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Board simulation"
+  it should "say goodbye " in {
+    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+

lab4/Makefile

@@ -24,8 +24,12 @@ verilator-sim: verilator
 
 basys3:
 	sbt "runMain board.basys3.VerilogGenerator"
+	
 pynq:
 	sbt "runMain board.pynq.VerilogGenerator"
+	
+z710:
+	sbt "runMain board.z710.VerilogGenerator"
 
 bitstream-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl
@@ -35,6 +39,7 @@ program-basys3: bitstream-basys3
 
 vivado-sim-basys3: basys3
 	cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl
+	
 bitstream-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl
 
@@ -43,5 +48,14 @@ program-pynq: bitstream-pynq
 
 vivado-sim-pynq: pynq
 	cd vivado/pynq && vivado -mode batch -source run_simulation.tcl
+	
+bitstream-z710: z710
+	cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl
 
-.PHONY: basys3 verilator test bitstream program verilator-sim vivado-sim
+program-z710: bitstream-z710
+	cd vivado/z710 && vivado -mode batch -source program_device.tcl
+
+vivado-sim-z710: z710
+	cd vivado/z710 && vivado -mode batch -source run_simulation.tcl
+
+.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim

lab4/src/main/scala/board/z710/z710/Top.scala

@@ -0,0 +1,119 @@
+package board.z710
+
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util._
+import chisel3.{ChiselEnum, _}
+
+// import circt.stage.ChiselStage
+import chisel3.stage.ChiselGeneratorAnnotation
+
+import bus._
+import peripheral._
+import riscv._
+import riscv.Parameters
+import riscv.core.CPU
+import javax.print.SimpleDoc
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, BusWait, Finished = Value
+}
+
+
+class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
+  // val binaryFilename = "say_goodbye.asmbin"
+  val io = IO(new Bundle {
+    // val switch = Input(UInt(16.W))
+
+    // val rgb = Output(UInt(12.W))
+
+    val led = Output(Bool())
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val uart = Module(new Uart(125_000_000, 115200))  // this freq is consistent with Zynq 7 PS UART module
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+
+  
+  val clock_freq = 100_000_000.U
+
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+
+  io.led := (led_count >= (clock_freq >> 1))
+
+
+}
+
+
+
+object VerilogGenerator extends App {
+    (new ChiselStage).execute(
+        Array("-X", "verilog", "--target-dir", "verilog/z710"), 
+        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
+    )
+    
+}

lab4/src/test/scala/riscv/BoardTest.scala

@@ -0,0 +1,25 @@
+package riscv
+
+import board.z710.Top
+
+import riscv.{Parameters, TestAnnotations}
+import chisel3._
+import chisel3.util.{is, switch}
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import board.z710.Top
+
+
+class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Board simulation"
+  it should "say goodbye " in {
+    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+