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TOKISAKIX\21168
2023-12-11 22:20:48 +08:00
parent e720a0dfc2
commit 2bce97ff4e
16 changed files with 635 additions and 11 deletions
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16
lab2/Makefile
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@@ -24,8 +24,12 @@ verilator-sim: verilator
basys3:
sbt "runMain board.basys3.VerilogGenerator"
pynq:
sbt "runMain board.pynq.VerilogGenerator"
z710:
sbt "runMain board.z710.VerilogGenerator"
bitstream-basys3: basys3
cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl
@@ -35,6 +39,7 @@ program-basys3: bitstream-basys3
vivado-sim-basys3: basys3
cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl
bitstream-pynq: pynq
cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl
@@ -43,5 +48,14 @@ program-pynq: bitstream-pynq
vivado-sim-pynq: pynq
cd vivado/pynq && vivado -mode batch -source run_simulation.tcl
bitstream-z710: z710
cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl
.PHONY: basys3 verilator test bitstream program verilator-sim vivado-sim
program-z710: bitstream-z710
cd vivado/z710 && vivado -mode batch -source program_device.tcl
vivado-sim-z710: z710
cd vivado/z710 && vivado -mode batch -source run_simulation.tcl
.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim