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temp fix for lab2 on z710v1.3 board

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PurplePower
2024-11-19 02:56:45 +08:00
parent b4141db235
commit 283eb09fd3
1 changed files with 5 additions and 1 deletions
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6
lab2/src/main/scala/board/z710v1.3/Top.scala
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@@ -63,7 +63,11 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
withClock(CPU_tick.asClock) {
val cpu = Module(new CPU)
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
// cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
/* disable interrupt flag for now, some unexpected bugs in Zybo 7010 v1.3 board*/
cpu.io.interrupt_flag := 0.U
cpu.io.csr_regs_debug_read_address := 0.U
cpu.io.regs_debug_read_address := 0.U
// cpu.io.debug_read_address := 0.U