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PurplePower
2024-11-18 23:17:58 +08:00
parent 93ac859c8f
commit 0f905afe36
11 changed files with 16 additions and 16 deletions
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BIN
lab2/src/main/resources/say_goodbye.asmbin
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12
lab2/src/main/scala/board/z710v1.3/Top.scala
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@@ -35,14 +35,14 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
val mem = Module(new Memory(Parameters.MemorySizeInWords))
// val hdmi_display = Module(new HDMIDisplay)
// val display = Module(new CharacterDisplay)
// val timer = Module(new Timer)
val timer = Module(new Timer)
val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error
val dummy = Module(new Dummy)
// display.io.bundle <> dummy.io.bundle
mem.io.bundle <> dummy.io.bundle
mem.io.debug_read_address := 0.U
// timer.io.bundle <> dummy.io.bundle
timer.io.bundle <> dummy.io.bundle
uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd
uart.io.rxd := io.rx
@@ -63,10 +63,10 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
withClock(CPU_tick.asClock) {
val cpu = Module(new CPU)
// cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
// cpu.io.csr_regs_debug_read_address := 0.U
// cpu.io.regs_debug_read_address := 0.U
cpu.io.debug_read_address := 0.U
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
cpu.io.csr_regs_debug_read_address := 0.U
cpu.io.regs_debug_read_address := 0.U
// cpu.io.debug_read_address := 0.U
// cpu.io.memory_bundle.read_data := 0.U
cpu.io.instruction_valid := rom_loader.io.load_finished
mem.io.instruction_address := cpu.io.instruction_address