From 0f87b85f9fbaa5d4e43781ccddb390a8829123a9 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Tue, 19 Nov 2024 00:50:11 +0800
Subject: [PATCH] update Top.scala for z710v1.3 in lab3 and lab4

---
 lab3/src/main/scala/board/z710v1.3/Top.scala |   2 +-
 lab4/src/main/scala/board/z710v1.3/Top.scala | 119 +++++++++++++++++++
 2 files changed, 120 insertions(+), 1 deletion(-)
 create mode 100644 lab4/src/main/scala/board/z710v1.3/Top.scala

diff --git a/lab3/src/main/scala/board/z710v1.3/Top.scala b/lab3/src/main/scala/board/z710v1.3/Top.scala
index 7496126..834c50a 100644
--- a/lab3/src/main/scala/board/z710v1.3/Top.scala
+++ b/lab3/src/main/scala/board/z710v1.3/Top.scala
@@ -97,7 +97,7 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
 
 object VerilogGenerator extends App {
   (new ChiselStage).execute(
-    Array("-X", "verilog", "-td", "verilog/z710"), 
+    Array("-X", "verilog", "-td", "verilog/z710v1.3"), 
     Seq(ChiselGeneratorAnnotation(() => new Top("say_goodbye.asmbin")))   // program to run on CPU
   )
 }
\ No newline at end of file
diff --git a/lab4/src/main/scala/board/z710v1.3/Top.scala b/lab4/src/main/scala/board/z710v1.3/Top.scala
new file mode 100644
index 0000000..6880f80
--- /dev/null
+++ b/lab4/src/main/scala/board/z710v1.3/Top.scala
@@ -0,0 +1,119 @@
+package board.z710
+
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util._
+import chisel3.{ChiselEnum, _}
+
+// import circt.stage.ChiselStage
+import chisel3.stage.ChiselGeneratorAnnotation
+
+import bus._
+import peripheral._
+import riscv._
+import riscv.Parameters
+import riscv.core.CPU
+import javax.print.SimpleDoc
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, BusWait, Finished = Value
+}
+
+
+class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
+  // val binaryFilename = "say_goodbye.asmbin"
+  val io = IO(new Bundle {
+    // val switch = Input(UInt(16.W))
+
+    // val rgb = Output(UInt(12.W))
+
+    val led = Output(Bool())
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+
+  })
+  val boot_state = RegInit(BootStates.Init)
+
+  val clock_freq = 50_000_000
+
+  val uart = Module(new Uart(clock_freq, 115200))
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val cpu = Module(new CPU)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val timer = Module(new Timer)
+  val dummy = Module(new DummySlave)
+  val bus_arbiter = Module(new BusArbiter)
+  val bus_switch = Module(new BusSwitch)
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  bus_arbiter.io.bus_request(0) := true.B
+
+  bus_switch.io.master <> cpu.io.axi4_channels
+  bus_switch.io.address := cpu.io.bus_address
+  for (i <- 0 until Parameters.SlaveDeviceCount) {
+    bus_switch.io.slaves(i) <> dummy.io.channels
+  }
+  rom_loader.io.load_address := Parameters.EntryAddress
+  rom_loader.io.load_start := false.B
+  rom_loader.io.rom_data := instruction_rom.io.data
+  instruction_rom.io.address := rom_loader.io.rom_address
+  cpu.io.stall_flag_bus := true.B
+  cpu.io.instruction_valid := false.B
+  bus_switch.io.slaves(0) <> mem.io.channels
+  rom_loader.io.channels <> dummy.io.channels
+  switch(boot_state) {
+    is(BootStates.Init) {
+      rom_loader.io.load_start := true.B
+      boot_state := BootStates.Loading
+      rom_loader.io.channels <> mem.io.channels
+    }
+    is(BootStates.Loading) {
+      rom_loader.io.load_start := false.B
+      rom_loader.io.channels <> mem.io.channels
+      when(rom_loader.io.load_finished) {
+        boot_state := BootStates.Finished
+      }
+    }
+    is(BootStates.Finished) {
+      cpu.io.stall_flag_bus := false.B
+      cpu.io.instruction_valid := true.B
+    }
+  }
+
+  bus_switch.io.slaves(2) <> uart.io.channels
+  bus_switch.io.slaves(4) <> timer.io.channels
+
+  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+
+  cpu.io.debug_read_address := 0.U
+  mem.io.debug_read_address := 0.U
+
+
+
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq.U) { // the led blinks every second, clock freq is 100M
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+
+  io.led := (led_count >= (clock_freq.U >> 1))
+
+
+}
+
+
+
+object VerilogGenerator extends App {
+    (new ChiselStage).execute(
+        Array("-X", "verilog", "--target-dir", "verilog/z710v1.3"), 
+        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
+    )
+    
+}
\ No newline at end of file