diff --git a/lab1/src/main/scala/board/z710/Top.scala b/lab1/src/main/scala/board/z710/Top.scala
index c98dd08..56c55d9 100644
--- a/lab1/src/main/scala/board/z710/Top.scala
+++ b/lab1/src/main/scala/board/z710/Top.scala
@@ -31,17 +31,17 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
   val mem = Module(new Memory(Parameters.MemorySizeInWords))
   // val hdmi_display = Module(new HDMIDisplay)
   // val display = Module(new CharacterDisplay)
-  // val timer = Module(new Timer)
-  // val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
+  val timer = Module(new Timer)
+  val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
   val dummy = Module(new Dummy)
 
   // display.io.bundle <> dummy.io.bundle
   mem.io.bundle <> dummy.io.bundle
   mem.io.debug_read_address := 0.U
-  // timer.io.bundle <> dummy.io.bundle
-  // uart.io.bundle <> dummy.io.bundle
-  // io.tx := uart.io.txd
-  // uart.io.rxd := io.rx
+  timer.io.bundle <> dummy.io.bundle
+  uart.io.bundle <> dummy.io.bundle
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
   io.tx := 0.U
 
   val instruction_rom = Module(new InstructionROM(binaryFilename))
@@ -60,26 +60,26 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
 
   withClock(CPU_tick.asClock) {
     val cpu = Module(new CPU)
-    // cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
-    // cpu.io.csr_regs_debug_read_address := 0.U
-    // cpu.io.regs_debug_read_address := 0.U
+    cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+    cpu.io.csr_regs_debug_read_address := 0.U
+    cpu.io.regs_debug_read_address := 0.U
     cpu.io.debug_read_address := 0.U
     // cpu.io.memory_bundle.read_data := 0.U
     cpu.io.instruction_valid := rom_loader.io.load_finished
     mem.io.instruction_address := cpu.io.instruction_address
     cpu.io.instruction := mem.io.instruction
 
-    // when(!rom_loader.io.load_finished) {
-    //   rom_loader.io.bundle <> mem.io.bundle
-    //   cpu.io.memory_bundle.read_data := 0.U
-    // }.otherwise {
-    //   rom_loader.io.bundle.read_data := 0.U
-    //   when(cpu.io.deviceSelect === 2.U) {
-    //     cpu.io.memory_bundle <> uart.io.bundle
-    //   }.otherwise {
-    //     cpu.io.memory_bundle <> mem.io.bundle
-    //   }
-    // }
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      when(cpu.io.deviceSelect === 2.U) {
+        cpu.io.memory_bundle <> uart.io.bundle
+      }.otherwise {
+        cpu.io.memory_bundle <> mem.io.bundle
+      }
+    }
 
     when(!rom_loader.io.load_finished) {
       rom_loader.io.bundle <> mem.io.bundle
diff --git a/lab1/vivado/z710/README.md b/lab1/vivado/z710/README.md
index 06390c5..bc0d7b9 100644
--- a/lab1/vivado/z710/README.md
+++ b/lab1/vivado/z710/README.md
@@ -80,6 +80,18 @@ set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse
 add_files -norecurse -fileset sources_1 $wrapper_path
 ```
 
+3. 修正脚本中使用了导出电脑上绝对路径的命令，在 `Adding sources referenced in BDs, if not already added`（Line 191）处使用的绝对路径替换为项目文件夹下相对路径。
+
+```tcl
+# Adding sources referenced in BDs, if not already added
+if { [get_files Top.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
+}
+if { [get_files clock_control.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
+}
+```
+
 修改后上述脚本就能重建项目。
 
 `open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。
diff --git a/lab2/vivado/z710/README.md b/lab2/vivado/z710/README.md
index 8ccaaef..dbb8773 100644
--- a/lab2/vivado/z710/README.md
+++ b/lab2/vivado/z710/README.md
@@ -80,6 +80,18 @@ set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse
 add_files -norecurse -fileset sources_1 $wrapper_path
 ```
 
+3. 修正脚本中使用了导出电脑上绝对路径的命令，在 `Adding sources referenced in BDs, if not already added`（Line 191）处使用的绝对路径替换为项目文件夹下相对路径。
+
+```tcl
+# Adding sources referenced in BDs, if not already added
+if { [get_files Top.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
+}
+if { [get_files clock_control.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
+}
+```
+
 修改后上述脚本就能重建项目。
 
 `open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。
diff --git a/lab3/vivado/z710/README.md b/lab3/vivado/z710/README.md
index 7ea982e..7a4ff61 100644
--- a/lab3/vivado/z710/README.md
+++ b/lab3/vivado/z710/README.md
@@ -80,6 +80,18 @@ set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse
 add_files -norecurse -fileset sources_1 $wrapper_path
 ```
 
+3. 修正脚本中使用了导出电脑上绝对路径的命令，在 `Adding sources referenced in BDs, if not already added`（Line 191）处使用的绝对路径替换为项目文件夹下相对路径。
+
+```tcl
+# Adding sources referenced in BDs, if not already added
+if { [get_files Top.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
+}
+if { [get_files clock_control.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
+}
+```
+
 修改后上述脚本就能重建项目。
 
 `open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。
diff --git a/lab4/vivado/z710/README.md b/lab4/vivado/z710/README.md
index 9c4e2ac..6d7f4d8 100644
--- a/lab4/vivado/z710/README.md
+++ b/lab4/vivado/z710/README.md
@@ -80,6 +80,18 @@ set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse
 add_files -norecurse -fileset sources_1 $wrapper_path
 ```
 
+3. 修正脚本中使用了导出电脑上绝对路径的命令，在 `Adding sources referenced in BDs, if not already added`（Line 191）处使用的绝对路径替换为项目文件夹下相对路径。
+
+```tcl
+# Adding sources referenced in BDs, if not already added
+if { [get_files Top.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
+}
+if { [get_files clock_control.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
+}
+```
+
 修改后上述脚本就能重建项目。
 
 `open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。