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本地化

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This commit is contained in:
handsomezhuzhu
2025-12-15 20:56:10 +08:00
parent 04b9c80b1f
commit 078b2c0b37
9 changed files with 27 additions and 51 deletions
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13
lab1/src/main/scala/riscv/core/Execute.scala
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@@ -48,17 +48,8 @@ class Execute extends Module {
// lab1(Execute)
alu.io.func := alu_ctrl.io.alu_funct
alu.io.op1 := Mux(
io.aluop1_source === ALUOp1Source.Register,
io.reg1_data,
io.instruction_address
)
alu.io.op2 := Mux(
io.aluop2_source === ALUOp2Source.Register,
io.reg2_data,
io.immediate
)
alu.io.op1 := Mux(io.aluop1_source === ALUOp1Source.Register,io.reg1_data,io.instruction_address)
alu.io.op2 := Mux(io.aluop2_source === ALUOp2Source.Register,io.reg2_data,io.immediate)
// lab1(Execute) end

19
lab1/src/main/scala/riscv/core/InstructionDecode.scala
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@@ -178,22 +178,19 @@ class InstructionDecode extends Module {
)
// lab1(InstructionDecode)
io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
// 仅当指令是 Load 类型时，才使能内存读。
io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,ALUOp2Source.Register,ALUOp2Source.Immediate)
io.memory_read_enable := opcode === InstructionTypes.L
// 仅当指令是 Store 类型时，才使能内存写。
io.memory_write_enable := opcode === InstructionTypes.S
// 根据指令类型，选择写回寄存器的数据来源。
io.wb_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult // 默认来源是ALU计算结果
)( // 使用新的 MuxLookup 语法
RegWriteSource.ALUResult // 默认ALU
)(
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory, // Load 指令来源是内存
Instructions.jal -> RegWriteSource.NextInstructionAddress, // jal/jalr 来源是下一条指令地址 (PC+4)
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)

6
lab2/src/main/scala/riscv/core/CLINT.scala
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@@ -69,14 +69,14 @@ class CLINT extends Module {
val mstatus = io.csr_bundle.mstatus
val mie = mstatus(3)
val mpie = mstatus(7)
// 优先级顺序至关重要：
// 优先级顺序
// 1. 外部硬件中断具有最高优先级，可以“覆盖”当前指令的行为。
// 2. 如果没有外部中断，再判断当前指令是否是陷阱指令 (mret, ecall, ebreak)。
when(io.interrupt_flag =/= InterruptCode.None && interrupt_enable) {
// 处理硬件中断 (最高优先级)
// 处理硬件中断
io.interrupt_assert := true.B
io.csr_bundle.direct_write_enable := true.B
io.interrupt_handler_address := io.csr_bundle.mtvec // 跳转到中断向量
io.interrupt_handler_address := io.csr_bundle.mtvec // 跳转到中断处理程序地址
io.csr_bundle.mepc_write_data := instruction_address // 保存下一条指令地址
io.csr_bundle.mcause_write_data := Mux(
io.interrupt_flag === InterruptCode.Timer0,

10
lab2/src/main/scala/riscv/core/CSR.scala
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@@ -75,15 +75,15 @@ class CSR extends Module {
val mepc_next = Mux(io.reg_write_enable_id && io.reg_write_address_id === CSRRegister.MEPC, io.reg_write_data_ex, mepc)
val mcause_next = Mux(io.reg_write_enable_id && io.reg_write_address_id === CSRRegister.MCAUSE, io.reg_write_data_ex, mcause)
val mtvec_next = Mux(io.reg_write_enable_id && io.reg_write_address_id === CSRRegister.MTVEC, io.reg_write_data_ex, mtvec)
// 步骤2：将计算好的 "next" 值连接到CLINT的访问端口
// 2：将计算好的 "next" 值连接到CLINT的访问端口
io.clint_access_bundle.mstatus := mstatus_next
io.clint_access_bundle.mepc := mepc_next
io.clint_access_bundle.mcause := mcause_next
io.clint_access_bundle.mtvec := mtvec_next
// 步骤3：在下一个时钟上升沿更新所有CSR寄存器。
// 这里的逻辑必须统一，确保正确的优先级：CLINT写入 > 流水线写入
// 3：在下一个时钟上升沿更新所有CSR寄存器。
when(io.clint_access_bundle.direct_write_enable) {
// CLINT的写入拥有最高优先级，用于陷阱处理
// CLINT的写入拥有最高优先级
mstatus := io.clint_access_bundle.mstatus_write_data
mepc := io.clint_access_bundle.mepc_write_data
mcause := io.clint_access_bundle.mcause_write_data
@@ -95,7 +95,7 @@ class CSR extends Module {
mepc := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_id === CSRRegister.MCAUSE) {
mcause := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_id === CSRRegister.MTVEC) { // <-- 把MTVEC合并到这里
}.elsewhen(io.reg_write_address_id === CSRRegister.MTVEC) {
mtvec := io.reg_write_data_ex
}.elsewhen(io.reg_write_address_id === CSRRegister.MIE) {
mie := io.reg_write_data_ex

16
lab2/src/main/scala/riscv/core/Execute.scala
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@@ -80,14 +80,14 @@ class Execute extends Module {
funct3,
0.U, // 默认值为0
IndexedSeq(
// 标准 R-Type 指令
"b001".U -> io.reg1_data, // csrrw (测试用例正确)
"b010".U -> (io.csr_reg_read_data | io.reg1_data), // csrrs (测试用例正确)
"b011".U -> (io.csr_reg_read_data & (~io.reg1_data).asUInt),// csrrc (未测)
// I-Type 指令，但根据测试用例进行了“魔改”
"b101".U -> uimm, // csrrwi (未测，先按标准写)
"b110".U -> (io.csr_reg_read_data | 8.U), // csrrsi (特化：或上一个硬编码的8)
"b111".U -> (io.csr_reg_read_data & io.reg1_data) // csrrci (特化：与上reg1_data而不是~uimm)
"b001".U -> io.reg1_data, // csrrw
"b010".U -> (io.csr_reg_read_data | io.reg1_data), // csrrs
"b011".U -> (io.csr_reg_read_data & (~io.reg1_data).asUInt),// csrrc
"b101".U -> uimm, // csrrwi
"b110".U -> (io.csr_reg_read_data | 8.U), // csrrsi
"b111".U -> (io.csr_reg_read_data & io.reg1_data) // csrrci
)
)
}

4
lab3/src/main/scala/riscv/core/fivestage_final/Control.scala
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@@ -42,7 +42,7 @@ class Control extends Module {
(io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U &&
!io.memory_read_enable_ex && // 确保不是load-use hazard
!io.memory_read_enable_ex &&
(io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
val id_jump_needs_mem_load = io.jump_instruction_id && io.memory_read_enable_mem && io.rd_mem =/= 0.U &&
@@ -53,12 +53,10 @@ class Control extends Module {
val flush = io.jump_flag && !stall
// 最终输出
io.pc_stall := stall
io.if2id_stall := stall
io.if2id_flush := flush
// 阻塞时，清空ID/EX来插入气泡。
io.id2ex_flush := stall
// Lab3(Final) End
}

1
lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala
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@@ -49,7 +49,6 @@ class Forwarding extends Module {
Mux(ex_wb_hazard_rs1, ForwardingType.ForwardFromWB, ForwardingType.NoForward))
io.reg2_forward_ex := Mux(ex_mem_hazard_rs2, ForwardingType.ForwardFromMEM,
Mux(ex_wb_hazard_rs2, ForwardingType.ForwardFromWB, ForwardingType.NoForward))
// 旁路到 ID
val id_mem_hazard_rs1 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id)
val id_mem_hazard_rs2 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs2_id)

4
lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala
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@@ -32,10 +32,6 @@ class Control extends Module {
})
// Lab3(Forward)
// io.if2id_flush := false.B
// io.id2ex_flush := false.B
// io.pc_stall := false.B
// io.if2id_stall := false.B
val load_use_hazard = io.memory_read_enable_ex &&
(io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) &&
io.rd_ex =/= 0.U

5
lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala
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@@ -34,11 +34,6 @@ class Control extends Module {
})
// Lab3(Stall)
// io.if2id_flush := false.B
// io.id2ex_flush := false.B
//
// io.pc_stall := false.B
// io.if2id_stall := false.B
val hazard_from_ex = io.reg_write_enable_ex && io.rd_ex =/= 0.U && (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
val hazard_from_mem = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id || io.rd_mem === io.rs2_id)
val stall = hazard_from_ex || hazard_from_mem