本地化

lab3/src/main/scala/riscv/core/fivestage_final/Control.scala

@@ -42,7 +42,7 @@ class Control extends Module {
     (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
 
   val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U &&
-    !io.memory_read_enable_ex && // 确保不是load-use hazard
+    !io.memory_read_enable_ex &&
     (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
 
   val id_jump_needs_mem_load = io.jump_instruction_id && io.memory_read_enable_mem && io.rd_mem =/= 0.U &&
@@ -53,12 +53,10 @@ class Control extends Module {
 
 
   val flush = io.jump_flag && !stall
-  // 最终输出
   io.pc_stall := stall
   io.if2id_stall := stall
   io.if2id_flush := flush
 
-  // 阻塞时，清空ID/EX来插入气泡。
   io.id2ex_flush := stall
   // Lab3(Final) End
 }

lab3/src/main/scala/riscv/core/fivestage_final/Forwarding.scala

@@ -49,7 +49,6 @@ class Forwarding extends Module {
     Mux(ex_wb_hazard_rs1, ForwardingType.ForwardFromWB, ForwardingType.NoForward))
   io.reg2_forward_ex := Mux(ex_mem_hazard_rs2, ForwardingType.ForwardFromMEM,
     Mux(ex_wb_hazard_rs2, ForwardingType.ForwardFromWB, ForwardingType.NoForward))
-  // 旁路到 ID
   val id_mem_hazard_rs1 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id)
   val id_mem_hazard_rs2 = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs2_id)
 

lab3/src/main/scala/riscv/core/fivestage_forward/Control.scala

@@ -32,10 +32,6 @@ class Control extends Module {
   })
 
   // Lab3(Forward)
-//  io.if2id_flush := false.B
-//  io.id2ex_flush := false.B
-//  io.pc_stall := false.B
-  //  io.if2id_stall := false.B
   val load_use_hazard = io.memory_read_enable_ex &&
     (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) &&
     io.rd_ex =/= 0.U

lab3/src/main/scala/riscv/core/fivestage_stall/Control.scala

@@ -34,11 +34,6 @@ class Control extends Module {
   })
 
   // Lab3(Stall)
-//  io.if2id_flush := false.B
-//  io.id2ex_flush := false.B
-//
-//  io.pc_stall := false.B
-//  io.if2id_stall := false.B
   val hazard_from_ex = io.reg_write_enable_ex && io.rd_ex =/= 0.U && (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
   val hazard_from_mem = io.reg_write_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id || io.rd_mem === io.rs2_id)
   val stall = hazard_from_ex || hazard_from_mem