zzh/2025-yatcpu
1
0
Fork 0
mirror of https://github.com/handsomezhuzhu/2025-yatcpu.git synced 2026-02-20 20:10:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

本地化

Browse Source
This commit is contained in:
handsomezhuzhu
2025-12-15 20:56:10 +08:00
parent 04b9c80b1f
commit 078b2c0b37
9 changed files with 27 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
lab1/src/main/scala/riscv/core/Execute.scala
View File

@@ -48,17 +48,8 @@ class Execute extends Module {
// lab1(Execute)
alu.io.func := alu_ctrl.io.alu_funct
alu.io.op1 := Mux(
io.aluop1_source === ALUOp1Source.Register,
io.reg1_data,
io.instruction_address
)
alu.io.op2 := Mux(
io.aluop2_source === ALUOp2Source.Register,
io.reg2_data,
io.immediate
)
alu.io.op1 := Mux(io.aluop1_source === ALUOp1Source.Register,io.reg1_data,io.instruction_address)
alu.io.op2 := Mux(io.aluop2_source === ALUOp2Source.Register,io.reg2_data,io.immediate)
// lab1(Execute) end

19
lab1/src/main/scala/riscv/core/InstructionDecode.scala
View File

@@ -178,22 +178,19 @@ class InstructionDecode extends Module {
)
// lab1(InstructionDecode)
io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,
ALUOp2Source.Register,
ALUOp2Source.Immediate
)
// 仅当指令是 Load 类型时，才使能内存读。
io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,ALUOp2Source.Register,ALUOp2Source.Immediate)
io.memory_read_enable := opcode === InstructionTypes.L
// 仅当指令是 Store 类型时，才使能内存写。
io.memory_write_enable := opcode === InstructionTypes.S
// 根据指令类型，选择写回寄存器的数据来源。
io.wb_reg_write_source := MuxLookup(
opcode,
RegWriteSource.ALUResult // 默认来源是ALU计算结果
)( // 使用新的 MuxLookup 语法
RegWriteSource.ALUResult // 默认ALU
)(
IndexedSeq(
InstructionTypes.L -> RegWriteSource.Memory, // Load 指令来源是内存
Instructions.jal -> RegWriteSource.NextInstructionAddress, // jal/jalr 来源是下一条指令地址 (PC+4)
InstructionTypes.L -> RegWriteSource.Memory,
Instructions.jal -> RegWriteSource.NextInstructionAddress,
Instructions.jalr -> RegWriteSource.NextInstructionAddress
)
)