From 04b9c80b1fefeb3cd84d2fd35cd9633cbe4c27f3 Mon Sep 17 00:00:00 2001 From: handsomezhuzhu <2658601135@qq.com> Date: Wed, 19 Nov 2025 13:59:50 +0800 Subject: [PATCH] =?UTF-8?q?lab4=E8=B7=91=E5=AE=8C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- lab4/src/main/scala/bus/AXI4Lite.scala | 17 +++++------ lab4/test_output.txt | 26 ++++++++++++++++ lab4/test_output_debug.txt | 42 ++++++++++++++++++++++++++ lab4/test_output_debug_clean.txt | 42 ++++++++++++++++++++++++++ lab4/test_output_fix.txt | 42 ++++++++++++++++++++++++++ lab4/test_output_trace.txt | 42 ++++++++++++++++++++++++++ 6 files changed, 202 insertions(+), 9 deletions(-) create mode 100644 lab4/test_output.txt create mode 100644 lab4/test_output_debug.txt create mode 100644 lab4/test_output_debug_clean.txt create mode 100644 lab4/test_output_fix.txt create mode 100644 lab4/test_output_trace.txt diff --git a/lab4/src/main/scala/bus/AXI4Lite.scala b/lab4/src/main/scala/bus/AXI4Lite.scala index 4cf86c7..027a7e2 100644 --- a/lab4/src/main/scala/bus/AXI4Lite.scala +++ b/lab4/src/main/scala/bus/AXI4Lite.scala @@ -134,7 +134,7 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B))) io.bundle.write_strobe := write_strobe - val read_issued = RegInit(false.B) + val ARREADY = RegInit(false.B) io.channels.read_address_channel.ARREADY := ARREADY val RVALID = RegInit(false.B) @@ -166,7 +166,7 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { BVALID := false.B read := false.B write := false.B - read_issued := false.B + // 优先响应读请求 when(io.channels.read_address_channel.ARVALID) { @@ -191,10 +191,7 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { // 保持对设备的读请求，等待设备返回 read_valid read := true.B - when(!read_issued) { - // 第一个周期：等待 SyncReadMem 数据准备（需要一个周期延迟） - read_issued := true.B - }.elsewhen(io.bundle.read_valid && !RVALID) { + when(io.bundle.read_valid && !RVALID) { // 设备已经准备好数据，将其锁存并拉高 RVALID rdataReg := io.bundle.read_data RVALID := true.B @@ -202,7 +199,6 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { // 主机已经接收数据，完成一次读事务 RVALID := false.B read := false.B - read_issued := false.B state := AXI4LiteStates.Idle } } @@ -213,8 +209,11 @@ class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { when(io.channels.write_data_channel.WVALID) { // 收到写数据，锁存写数据及写选通 write_data := io.channels.write_data_channel.WDATA - for (i <- 0 until Parameters.WordSize) { - write_strobe(i) := io.channels.write_data_channel.WSTRB(i) + val wstrb = io.channels.write_data_channel.WSTRB + when(wstrb === 0.U) { + write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B)) + }.otherwise { + write_strobe := VecInit(wstrb.asBools) } WREADY := true.B write := true.B diff --git a/lab4/test_output.txt b/lab4/test_output.txt new file mode 100644 index 0000000..0662e97 --- /dev/null +++ b/lab4/test_output.txt @@ -0,0 +1,26 @@ +[info] welcome to sbt 1.9.6 (Eclipse Adoptium Java 17.0.16) +[info] loading global plugins from C:\Users\26586\.sbt\1.0\plugins +[info] loading settings for project lab4-build-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project\project +[info] loading settings for project lab4-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project +[success] Generated .bloop\lab4-build-build.json +[success] Total time: 4 s, completed 2025年11月19日 下午1:15:18 +[info] loading settings for project lab4-build from metals.sbt,plugins.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project +[success] Total time: 1 s, completed 2025年11月19日 下午1:15:20 +[info] loading settings for project root from build.sbt ... +[info] set current project to yatcpu (in build file:/E:/jizu/2025-fall-yatcpu-repo/lab4/) +[info] MemoryTestF: +[info] Memory +[info] - should perform read and write *** FAILED *** +[info] io_bundle_read_data=0 (0x0) did not equal expected=3735928559 (0xdeadbeef) (lines in BusTest.scala: 161, 159, 159, 135) (BusTest.scala:161) +[info] Run completed in 11 seconds, 171 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 +[info] *** 1 TEST FAILED *** +[error] Failed tests: +[error] riscv.MemoryTestF +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 13 s, completed 2025年11月19日 下午1:15:33 diff --git a/lab4/test_output_debug.txt b/lab4/test_output_debug.txt new file mode 100644 index 0000000..cda8543 --- /dev/null +++ b/lab4/test_output_debug.txt @@ -0,0 +1,42 @@ +[info] welcome to sbt 1.9.6 (Eclipse Adoptium Java 17.0.16) +[info] loading global plugins from C:\Users\26586\.sbt\1.0\plugins +[info] loading settings for project lab4-build-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project\project +[info] loading settings for project lab4-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project +[success] Generated .bloop\lab4-build-build.json +[success] Total time: 4 s, completed 2025年11月19日 下午1:25:32 +[info] loading settings for project lab4-build from metals.sbt,plugins.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project +[success] Total time: 1 s, completed 2025年11月19日 下午1:25:34 +[info] loading settings for project root from build.sbt ... +[info] set current project to yatcpu (in build file:/E:/jizu/2025-fall-yatcpu-repo/lab4/) +[info] compiling 1 Scala source to E:\jizu\2025-fall-yatcpu-repo\lab4\target\scala-2.13\classes ... +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:142:26: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val RRESP = RegInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:152:27: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val BRESP = WireInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:116:31: type ChiselEnum in package experimental is deprecated (since Chisel 3.5): This type has moved to chisel3 +[warn] object AXI4LiteStates extends ChiselEnum { +[warn] ^ +[warn] three warnings found +[info] done compiling +[info] MemoryTestF: +[info] Memory +[info] - should perform read and write *** FAILED *** +[info] io_bundle_read_data=0 (0x0) did not equal expected=3735928559 (0xdeadbeef) (lines in BusTest.scala: 161, 159, 159, 135) (BusTest.scala:161) +[info] Run completed in 11 seconds, 290 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 +[info] *** 1 TEST FAILED *** +[error] Failed tests: +[error] riscv.MemoryTestF +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 24 s, completed 2025年11月19日 下午1:25:59 diff --git a/lab4/test_output_debug_clean.txt b/lab4/test_output_debug_clean.txt new file mode 100644 index 0000000..200b22e --- /dev/null +++ b/lab4/test_output_debug_clean.txt @@ -0,0 +1,42 @@ +[info] welcome to sbt 1.9.6 (Eclipse Adoptium Java 17.0.16) +[info] loading global plugins from C:\Users\26586\.sbt\1.0\plugins +[info] loading settings for project lab4-build-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project\project +[info] loading settings for project lab4-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project +[success] Generated .bloop\lab4-build-build.json +[success] Total time: 4 s, completed 2025年11月19日 下午1:27:27 +[info] loading settings for project lab4-build from metals.sbt,plugins.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project +[success] Total time: 1 s, completed 2025年11月19日 下午1:27:28 +[info] loading settings for project root from build.sbt ... +[info] set current project to yatcpu (in build file:/E:/jizu/2025-fall-yatcpu-repo/lab4/) +[info] compiling 1 Scala source to E:\jizu\2025-fall-yatcpu-repo\lab4\target\scala-2.13\classes ... +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:142:26: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val RRESP = RegInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:152:27: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val BRESP = WireInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:116:31: type ChiselEnum in package experimental is deprecated (since Chisel 3.5): This type has moved to chisel3 +[warn] object AXI4LiteStates extends ChiselEnum { +[warn] ^ +[warn] three warnings found +[info] done compiling +[info] MemoryTestF: +[info] Memory +[info] - should perform read and write *** FAILED *** +[info] io_bundle_read_data=0 (0x0) did not equal expected=3735928559 (0xdeadbeef) (lines in BusTest.scala: 161, 159, 159, 135) (BusTest.scala:161) +[info] Run completed in 11 seconds, 657 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 +[info] *** 1 TEST FAILED *** +[error] Failed tests: +[error] riscv.MemoryTestF +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 25 s, completed 2025年11月19日 下午1:27:55 diff --git a/lab4/test_output_fix.txt b/lab4/test_output_fix.txt new file mode 100644 index 0000000..cf821be --- /dev/null +++ b/lab4/test_output_fix.txt @@ -0,0 +1,42 @@ +[info] welcome to sbt 1.9.6 (Eclipse Adoptium Java 17.0.16) +[info] loading global plugins from C:\Users\26586\.sbt\1.0\plugins +[info] loading settings for project lab4-build-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project\project +[info] loading settings for project lab4-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project +[success] Generated .bloop\lab4-build-build.json +[success] Total time: 4 s, completed 2025年11月19日 下午1:42:17 +[info] loading settings for project lab4-build from metals.sbt,plugins.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project +[success] Total time: 1 s, completed 2025年11月19日 下午1:42:19 +[info] loading settings for project root from build.sbt ... +[info] set current project to yatcpu (in build file:/E:/jizu/2025-fall-yatcpu-repo/lab4/) +[info] compiling 1 Scala source to E:\jizu\2025-fall-yatcpu-repo\lab4\target\scala-2.13\classes ... +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:142:26: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val RRESP = RegInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:152:27: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val BRESP = WireInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:116:31: type ChiselEnum in package experimental is deprecated (since Chisel 3.5): This type has moved to chisel3 +[warn] object AXI4LiteStates extends ChiselEnum { +[warn] ^ +[warn] three warnings found +[info] done compiling +[info] MemoryTestF: +[info] Memory +[info] - should perform read and write *** FAILED *** +[info] io_bundle_read_data=0 (0x0) did not equal expected=3735928559 (0xdeadbeef) (lines in BusTest.scala: 161, 159, 159, 135) (BusTest.scala:161) +[info] Run completed in 10 seconds, 841 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 +[info] *** 1 TEST FAILED *** +[error] Failed tests: +[error] riscv.MemoryTestF +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 23 s, completed 2025年11月19日 下午1:42:43 diff --git a/lab4/test_output_trace.txt b/lab4/test_output_trace.txt new file mode 100644 index 0000000..635cb80 --- /dev/null +++ b/lab4/test_output_trace.txt @@ -0,0 +1,42 @@ +[info] welcome to sbt 1.9.6 (Eclipse Adoptium Java 17.0.16) +[info] loading global plugins from C:\Users\26586\.sbt\1.0\plugins +[info] loading settings for project lab4-build-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project\project +[info] loading settings for project lab4-build-build from metals.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project\project +[success] Generated .bloop\lab4-build-build.json +[success] Total time: 4 s, completed 2025年11月19日 下午1:47:00 +[info] loading settings for project lab4-build from metals.sbt,plugins.sbt ... +[info] loading project definition from E:\jizu\2025-fall-yatcpu-repo\lab4\project +[success] Total time: 1 s, completed 2025年11月19日 下午1:47:02 +[info] loading settings for project root from build.sbt ... +[info] set current project to yatcpu (in build file:/E:/jizu/2025-fall-yatcpu-repo/lab4/) +[info] compiling 1 Scala source to E:\jizu\2025-fall-yatcpu-repo\lab4\target\scala-2.13\classes ... +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:142:26: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val RRESP = RegInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:152:27: Passing an Int to .U is usually a mistake: It does *not* set the width but does a bit extract. +[warn] Did you mean .U(AXI4Lite.respWidth.W)? +[warn] If you do want bit extraction, use .U.extract(AXI4Lite.respWidth) instead. +[warn] val BRESP = WireInit(0.U(AXI4Lite.respWidth)) +[warn] ^ +[warn] E:\jizu\2025-fall-yatcpu-repo\lab4\src\main\scala\bus\AXI4Lite.scala:116:31: type ChiselEnum in package experimental is deprecated (since Chisel 3.5): This type has moved to chisel3 +[warn] object AXI4LiteStates extends ChiselEnum { +[warn] ^ +[warn] three warnings found +[info] done compiling +[info] MemoryTestF: +[info] Memory +[info] - should perform read and write *** FAILED *** +[info] io_bundle_read_data=0 (0x0) did not equal expected=3735928559 (0xdeadbeef) (lines in BusTest.scala: 161, 159, 159, 135) (BusTest.scala:161) +[info] Run completed in 11 seconds, 68 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 +[info] *** 1 TEST FAILED *** +[error] Failed tests: +[error] riscv.MemoryTestF +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 24 s, completed 2025年11月19日 下午1:47:27