{
  "design": {
    "design_info": {
      "boundary_crc": "0xD2682A7282870375",
      "device": "xc7z010clg400-1",
      "name": "design_1",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2020.1",
      "validated": "true"
    },
    "design_tree": {
      "processing_system7_0": "",
      "clock_control_0": "",
      "xlconstant_0": "",
      "Top_0": ""
    },
    "interface_ports": {
      "DDR": {
        "mode": "Master",
        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "TIMEPERIOD_PS": {
            "value": "1250",
            "value_src": "default"
          },
          "MEMORY_TYPE": {
            "value": "COMPONENTS",
            "value_src": "default"
          },
          "DATA_WIDTH": {
            "value": "8",
            "value_src": "default"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_MASK_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "default"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "default"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "default"
          },
          "AXI_ARBITRATION_SCHEME": {
            "value": "TDM",
            "value_src": "default"
          },
          "CAS_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "default"
          }
        }
      },
      "FIXED_IO": {
        "mode": "Master",
        "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          }
        }
      }
    },
    "ports": {
      "io_clock": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "design_1_clock",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.000",
            "value_src": "default"
          }
        }
      },
      "io_alive_led": {
        "direction": "O"
      },
      "io_reset": {
        "direction": "I",
        "parameters": {
          "POLARITY": {
            "value": "",
            "value_src": "weak"
          }
        }
      },
      "enable_clk": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "design_1_enable_clk_0",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.000",
            "value_src": "default"
          }
        }
      }
    },
    "components": {
      "processing_system7_0": {
        "vlnv": "xilinx.com:ip:processing_system7:5.5",
        "xci_name": "design_1_processing_system7_0_0",
        "parameters": {
          "PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
            "value": "666.666687"
          },
          "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
            "value": "10.158730"
          },
          "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
            "value": "50.000000"
          },
          "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
            "value": "200.000000"
          },
          "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
            "value": "10.000000"
          },
          "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
            "value": "200.000000"
          },
          "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
            "value": "100.000000"
          },
          "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
            "value": "111.111115"
          },
          "PCW_CLK0_FREQ": {
            "value": "50000000"
          },
          "PCW_CLK1_FREQ": {
            "value": "10000000"
          },
          "PCW_CLK2_FREQ": {
            "value": "10000000"
          },
          "PCW_CLK3_FREQ": {
            "value": "10000000"
          },
          "PCW_DDR_RAM_HIGHADDR": {
            "value": "0x1FFFFFFF"
          },
          "PCW_EN_EMIO_UART0": {
            "value": "1"
          },
          "PCW_EN_UART0": {
            "value": "1"
          },
          "PCW_EN_UART1": {
            "value": "1"
          },
          "PCW_FPGA_FCLK0_ENABLE": {
            "value": "1"
          },
          "PCW_MIO_48_IOTYPE": {
            "value": "LVCMOS 3.3V"
          },
          "PCW_MIO_48_PULLUP": {
            "value": "enabled"
          },
          "PCW_MIO_48_SLEW": {
            "value": "slow"
          },
          "PCW_MIO_49_IOTYPE": {
            "value": "LVCMOS 3.3V"
          },
          "PCW_MIO_49_PULLUP": {
            "value": "enabled"
          },
          "PCW_MIO_49_SLEW": {
            "value": "slow"
          },
          "PCW_MIO_TREE_PERIPHERALS": {
            "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
          },
          "PCW_MIO_TREE_SIGNALS": {
            "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
          },
          "PCW_UART0_GRP_FULL_ENABLE": {
            "value": "0"
          },
          "PCW_UART0_PERIPHERAL_ENABLE": {
            "value": "1"
          },
          "PCW_UART0_UART0_IO": {
            "value": "EMIO"
          },
          "PCW_UART1_GRP_FULL_ENABLE": {
            "value": "0"
          },
          "PCW_UART1_PERIPHERAL_ENABLE": {
            "value": "1"
          },
          "PCW_UART1_UART1_IO": {
            "value": "MIO 48 .. 49"
          },
          "PCW_UART_PERIPHERAL_FREQMHZ": {
            "value": "100"
          },
          "PCW_UART_PERIPHERAL_VALID": {
            "value": "1"
          },
          "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
            "value": "533.333374"
          },
          "PCW_USE_M_AXI_GP0": {
            "value": "0"
          }
        }
      },
      "clock_control_0": {
        "vlnv": "xilinx.com:module_ref:clock_control:1.0",
        "xci_name": "design_1_clock_control_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "clock_control",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clk_in": {
            "direction": "I",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_clock",
                "value_src": "default_prop"
              },
              "FREQ_HZ": {
                "value": "100000000",
                "value_src": "user_prop"
              },
              "PHASE": {
                "value": "0.000",
                "value_src": "default_prop"
              }
            }
          },
          "enable_clk": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_enable_clk_0",
                "value_src": "default_prop"
              }
            }
          },
          "clk_out": {
            "direction": "O",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "",
                "value_src": "weak"
              },
              "FREQ_HZ": {
                "value": "",
                "value_src": "weak"
              },
              "PHASE": {
                "value": "",
                "value_src": "weak"
              }
            }
          }
        }
      },
      "xlconstant_0": {
        "vlnv": "xilinx.com:ip:xlconstant:1.1",
        "xci_name": "design_1_xlconstant_0_0"
      },
      "Top_0": {
        "vlnv": "xilinx.com:module_ref:Top:1.0",
        "xci_name": "design_1_Top_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "Top",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clock": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "reset",
                "value_src": "constant"
              }
            }
          },
          "reset": {
            "type": "rst",
            "direction": "I"
          },
          "io_tx": {
            "direction": "O"
          },
          "io_rx": {
            "direction": "I"
          },
          "io_led": {
            "direction": "O"
          }
        }
      }
    },
    "interface_nets": {
      "processing_system7_0_FIXED_IO": {
        "interface_ports": [
          "FIXED_IO",
          "processing_system7_0/FIXED_IO"
        ]
      },
      "processing_system7_0_DDR": {
        "interface_ports": [
          "DDR",
          "processing_system7_0/DDR"
        ]
      }
    },
    "nets": {
      "Top_0_io_tx": {
        "ports": [
          "Top_0/io_tx",
          "processing_system7_0/UART0_RX"
        ]
      },
      "Top_0_io_led": {
        "ports": [
          "Top_0/io_led",
          "io_alive_led"
        ]
      },
      "io_reset_1": {
        "ports": [
          "io_reset",
          "Top_0/reset"
        ]
      },
      "io_clock_1": {
        "ports": [
          "io_clock",
          "clock_control_0/clk_in"
        ]
      },
      "enable_clk_0_1": {
        "ports": [
          "enable_clk",
          "clock_control_0/enable_clk"
        ]
      },
      "clock_control_0_clk_out": {
        "ports": [
          "clock_control_0/clk_out",
          "Top_0/clock"
        ]
      },
      "xlconstant_0_dout": {
        "ports": [
          "xlconstant_0/dout",
          "Top_0/io_rx"
        ]
      }
    }
  }
}